AMD Elan SC520, User Manual, Page: 177 / 444

PCI Bus Host Bridge
Élan™SC520 Microcontroller User’s Manual 9-29
The concurrent nature of ÉlanSC520 microcontroller’s system architecture is such that a
SDRAM read request from an external PCI master may be delayed. The reasons for this
delay are:
■ The Am5
x
86 CPU may be currently accessing ROM, GP bus, or SDRAM.
■
The SDRAM controller may be currently servicing a SDRAM refresh.
■ A DMA transaction may be in progress between a GP-DMA initiator and SDRAM. Such
transactions are variable in length and subject to the programmed DMA transfer mode.
For example, in block or demand mode, the DMA transfer cannot be preempted.
Note: Large GP Bus DMA transfers in demand or block mode, or very slow GP bus cycles
(initiated via programmable GP bus timing, or by deasserting the GPRDY signal) can cause
the PCI host bridge target controller to violate the 10 µs memory write maximum completion
time limit set in the PCI Local Bus Specification, Revision 2.2. In PCI bus 2.2-compliant
designs, software must limit the length of GP bus cycles and GP bus DMA demand- or
block-mode transfers.
Delayed transactions can increase Am5
x
86 CPU and GP-DMA latency to SDRAM because
of prefetching in response to memory-read-multiple commands. For example, when a
prefetch of 64 doublewords occurs during a PCI bus master memory-read-multiple cycle
of the ÉlanSC520 microcontroller’s SDRAM, neither the Am5
x
86 CPU or the GP-DMA
controller has access to the CPU bus. After the initial prefetch of 64 doublewords, the PCI
host bridge relinquishes ownership of the CPU bus.
9.6 INITIALIZATION
The PCI bus RST signal, when asserted, resets the ÉlanSC520 microcontroller’s PCI host
bridge, as well as any external PCI bus devices.
The RST signal is asserted in response to a system reset (see “System Reset” on page 6-4)
or by setting the PCI_RST bit in the Host Bridge Control (HBCTL) register (MMCR offset
60h). These reset sources assert and deassert the RST signal asynchronously to the PCI
bus clock.
When the RST signal is asserted, the PCI host bridge master controller and target controller
state machines go to their idle states, and the host bridge FIFOs are purged. The PCI host
bridge register bits are reset to their default states due to system reset, but the PCI_RST
bit does not reset the PCI host bridge configuration registers or the host bridge status bits
(see the register descriptions in the
Élan™SC520 Microcontroller Register Set Manual,
order #22005).
After reset, the PCI host bridge target controller is disabled, but the host bridge responds
to configuration transactions from the Am5
x
86 CPU. Note that the PCI host bridge master
controller is always enabled.
After reset the following steps should be taken to configure the PCI host bridge. Configure
the PCI host bridge first; then, configure the external PCI bus devices.
1. Configure the PCI host bridge.
a. Program the desired ÉlanSC520 microcontroller arbitration mode, including
concurrency mode and PCI bus master arbitration priorities, etc. See “Initialization”
on page 8-22, for more detailed information on arbitration.
b. Program the Programmable Address Region (PAR) registers, if required. See
Chapter 4, “System Address Mapping”, for details on programming PCI bus memory
space.