AMD Elan SC520, User Manual, Page: 213 / 444

SDRAM Controller
Élan™SC520 Microcontroller User’s Manual 10-35
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The final address must have processor address bits 27–24 all off.
There are many addresses which meet this criteria, of which one example is:
address5 = 0F000000h
address6 = 07000000h
address7 = 03000000h
address8 = 01000000h
address9 = 00000000h
Here is the sequence to determine the correct number of internal banks:
1. First, pattern5 is written and read back from address5.
2. Pattern6 is written and read back from address6.
3. Pattern7 is written and read back from address7.
4. Pattern8 is written and read back from address8.
5. Pattern9 is written and read back from address9.
6. If any of these five reads fail to produce the same pattern that was written, then either
SDRAM does not exist for this external bank, or the SDRAM is nonfunctional, which in
either case no memory is enabled and sizing continues with the next external bank.
7. If all five reads are correct, then the correct number of internal banks can be determined
by reading address7 once again.
8. If the pattern read from address7 is pattern9, then only two internal banks exist for this
external bank.
9. If the pattern read from address7 is pattern7 or pattern8, then four internal banks exist.
10.If the pattern read from address7 is anything other than pattern7, pattern8, or pattern9,
then there is no valid memory for this external bank.
The reason pattern7 is read back from a 2-internal-bank SDRAM is because the SDRAM
controller thinks it has two open pages, and the SDRAM has only one open page, so the
data is retrieved erroneously from the wrong page.
10.6.4.3 Determining the True External Bank Ending Address
The true ending address can now be determined by reading adress5 again. If any value
other than pattern5, pattern6, pattern7, or pattern8 is read, then there is no valid memory
for this external bank.
Here is the sequence to determine the true external bank ending address:
1. Using the values for these patterns as in the example, the value read represents the
ending address for the external bank, if the device has 11 columns.
2. So, this value must be shifted right by the value 11, minus the actual number of columns
determined to exist.
3. This value must then be incremented by 1 and ORed with 80h to be ready to be loaded
into the appropriate byte of the SDRAM Bank 0–3 Ending Address (DRCBENDADR)
register (MMCR offset 18h).
This process is continued until all four possible external banks have been checked.