AMD Elan SC520, User Manual, Page: 353 / 444

UART Serial Ports
Élan™SC520 Microcontroller User’s Manual 21-7
The Transmitter Empty (TEMT) bit in the UART x Line Status (UARTxLSR) register is set
in this mode if both the UART x Transmit Holding (UARTxTHR) register and internal
transmitter shift register are empty. An application could write two bytes consecutively to
the UART x Transmit Holding (UARTxTHR) register without checking THRE if TEMT is
detected as set.
21.5.1.2 16550-Compatible UART Mode
In 16550-compatible (FIFO) mode:
1. Data written to the UART x Transmit Holding (UARTxTHR) register address is latched
into the next available FIFO location.
2. The transmit data is shifted directly out of the first FIFO entry with valid data. There are
a total of 16 bytes in the FIFO. Thus, if the TEMT bit is set, then software can safely
write 16 bytes consecutively to the UART x Transmit Holding (UARTxTHR) register
address for transmission.
The THRE (which can optionally generate an interrupt) and TEMT bits are set whenever
the last character is shifted from the FIFO and the FIFO becomes empty. If the number of
characters currently in the FIFO is unknown, software should wait for the THRE or TEMT
bit to be set before writing additional data.
21.5.2 Data Reception
21.5.2.1 16450-Compatible UART Mode
In 16450-compatible mode:
1. Received data is shifted from the SIN pin into the internal receive shift register.
2. Once an entire UART frame has been received, the character is transferred from the
internal receive shift register into the UART x Receive Buffer (UARTxRBR) register.
3. The Data Ready (DR) bit in the UART x Line Status (UARTxLSR) register is set to 1
(optionally generating an interrupt).
Note that the DR bit is cleared by a read of the UART x Receive Buffer (UARTxRBR) register.
If a second character is transferred into the UART x Receive Buffer (UARTxRBR) register
before software reads the first one (i.e., the DR bit is still set), then the Overrun Error (OE)
bit in the UART x Line Status (UARTxLSR) register is set to 1, and the first character is
destroyed. Subsequent received bytes continue to overwrite the UART x Receive Buffer
(UARTxRBR) register until software reads the UART x Receive Buffer (UARTxRBR)
register.
21.5.2.2 16550-Compatible UART Mode
In 16550-compatible mode:
1. Received data is shifted into the internal receive shift register.
2. Once an entire UART frame has been received, the character is transferred from the
internal receive shift register into the FIFO.
– If the FIFO was empty, the DR bit in the UART x Line Status (UARTxLSR) register is
set and remains set until the FIFO is completely emptied by software.
– If the received character places the FIFO above the limit indicated by the RFRT field
in the UART x FIFO Control (UARTxFCR) register and received data available
interrupts are enabled, then an interrupt is generated.
– A received data available interrupt also occurs if data is present in the FIFO and no
software reads have removed data from the receive FIFO in four character times. In