AMD Elan SC520, User Manual, Page: 136 / 444

System Arbitration
8-12 Élan™SC520 Microcontroller User’s Manual
cpu_hold to the Am5
x
86 CPU would remain asserted. In this example, another CPU bus
master also requests the bus by asserting mst_req.
■
Clock #3: The Am5
x
86 CPU samples cpu_hold deasserted and deasserts cpu_hlda to
take ownership of the bus. The Am5
x
86 CPU begins a cycle by asserting cpu_ads.
■
Clock #4: The CPU bus arbiter samples cpu_ads asserted and rearbitrates. The CPU
bus arbiter determines that the bus will be granted to another master (CPU bus master)
when the current cycle is done, so it asserts cpu_hold to the Am5
x
86 CPU. The Am5
x
86
CPU will maintain ownership of the bus until it asserts cpu_hlda.
■
Clock #8: The Am5
x
86 CPU samples cpu_rdy asserted, which ends the current cycle.
The Am5
x
86 CPU has also sampled cpu_hold asserted and surrenders the bus by
asserting cpu_hlda. The Am5
x
86 CPU has another cycle pending, so it asserts cpu_breq
to request access to the CPU bus.
■
Clock #9: The CPU bus arbiter samples cpu_hlda asserted from the Am5
x
86 CPU and
grants the bus to the CPU bus master (the next master in the queue) by asserting mst_gnt
to the CPU bus master.
■ Clock #10: The CPU bus master samples mst_gnt asserted and begins a cycle by
asserting mst_ads.
■ Clock #11: The CPU bus arbiter samples mst_ads asserted and rearbitrates. The CPU
bus arbiter determines that the bus will be granted to the Am5
x
86 CPU when the current
cycle is done, so it deasserts mst_gnt to the CPU bus master. The CPU bus master will
maintain ownership of the bus until it deasserts mst_req.
■ Clock #15: The CPU bus master samples mst_rdy asserted, which ends the current
cycle. The CPU bus master also samples mst_gnt deasserted and surrenders the bus
by deasserting mst_req.
■
Clock #16: The CPU bus arbiter samples mst_gnt deasserted from the CPU bus master,
and grants the bus to the Am5
x
86 CPU by deasserting cpu_hold.
8.4.4.2 CPU Bus Cache Write-Back
Figure 8-7 shows an Am5
x
86 CPU cache write-back cycle. The cache must be written back
when another CPU bus master accesses a memory location that has been modified in the
internal Am5
x
86 CPU cache only (the external memory contains invalid data).