AMD Elan SC520, User Manual, Page: 79 / 444

Élan™SC520 Microcontroller User’s Manual 4-1
CHAPTER
4
SYSTEM ADDRESS MAPPING
4.1 OVERVIEW
The ÉlanSC520 microcontroller includes flexible memory and I/O address decoding with
features for both real-time operating systems (RTOS) and systems requiring PC/AT
functionality for Windows
compatibility. Address decoding is distributed between the
memory controllers, GP bus controller, and PCI host bridge controller. The ÉlanSC520
microcontroller provides the following memory and I/O address mapping options.
■ The default SDRAM map is linear space starting at 00000000h through the top of
SDRAM (defined by the total size of the SDRAM array, up to a maximum of 256 Mbytes).
■ The default boot ROM/Flash chip select (BOOTCS pin) is mapped in a 64-Kbyte linear
region at the top of CPU memory space from FFFF0000–FFFFFFFFh, and this entire
ROM space can be redirected through configuration registers (address translation is not
supported).
■ All configuration registers that do not reside in PC/AT I/O space or PCI configuration
space are memory-mapped and are located in a 4-Kbyte region in memory address
space from FFFEF000–FFFEFFFFh.
– This 4-Kbyte region is called the
memory-mapped configuration region (MMCR).
– The MMCR can optionally be relocated on any 4-Kbyte boundary in the lower 1-Gbyte
region via an I/O mapped register called the Configuration Base Address (CBAR)
register (Port FFFCh).
– The default MMCR region in high memory (below the boot space) is visible even if it
is aliased via the Configuration Base Address (CBAR) register.
■
The default PCI bus map is contiguous space starting directly above the top of SDRAM
through 4 Gbytes, minus the 68 Kbytes for the boot ROM/Flash region and the MMCR.
■
16 general-purpose Programmable Address Region (PAR) windows allow address
mapping for a variety of applications, including operating systems requiring x86 real
mode support. Each window allows any memory region in the lower 1-Gbyte region to
be directed to the following resources:
– Any of three ROM chip-selects with the ability to apply cacheability, write-protection,
and nonexecutable region attributes
– Any of eight GP bus chip-selects for external memory or I/O peripherals on the GP bus
– Two PAR registers allow cycles to be forwarded to the PCI bus for applications that
require PCI space to be overlaid on top of SDRAM. All accesses above the top of
SDRAM to the top of 32-bit memory space are
automatically forwarded to PCI bus
(with the exception of the ROM boot space and memory-mapped configuration space).
– Accesses in normal SDRAM space (lower 256 Mbytes) can also be redirected to ROM,
the GP bus, or the PCI bus.
– PAR windows can be created in the SDRAM region to allow noncacheable, write-
protected, and/or nonexecutable buffers.