AMD Elan SC520, User Manual, Page: 284 / 444

GP Bus DMA Controller
14-18 Élan™SC520 Microcontroller User’s Manual
14.5.7 Clocking Considerations
The GP-DMA controller can be programmed to operate at 4 MHz, 8 MHz, or 16 MHz. This
option is specified in the GP-DMA Control (GPDMACTL) register (MMCR offset D80h).
Note that these frequencies are derived from the 33-MHz clock. The exact frequency is an
even fraction of the crystal (33.000-MHz or 33.333-MHz) being used in the system.
14.5.8 Interrupts
In normal GP-DMA mode, the GP-DMA controller does not generate interrupts, but it does
assert GPTC upon the completion of every transfer.
When buffer chaining mode is enabled, the GP-DMA controller generates a maskable or
non-maskable interrupt every time a buffer is completely transferred. This interrupt is
generated after the valid values of the Next Address and Next Transfer Count are loaded
into the internal current address and current transfer count registers, respectively. GPTC
is asserted only when there is no other buffer in the chain. When GPTC is asserted, the
interrupt is still generated.
14.5.9 Software Considerations
Channel 4 must always be set to be in cascade mode; otherwise, erroneous operation may
result.
Only Channel 4 should be programmed for cascade mode. All other channels should
be programmed to be in one of the other three modes (single, demand or block).
The Memory Address and Transfer Count registers of each channel are byte-accessed.
Two consecutive byte reads or writes to the same I/O address are required when accessing
the 16-bit values of these registers. In enhanced GP-DMA mode, although the Next Address
registers and the Next Transfer Count registers are both split up into two 16-bit registers,
the Low and High words have been placed so that they can be accessed using 32-bit
instructions. Although the GP bus splits 32-bit accesses up into two 16-bit accesses (i.e.,
the setting of the low and high address will be nonatomic), this should not typically cause
any problems.
When using the buffer chaining feature in block transfer mode, the GP-DMA controller
continues to hold the bus request until the second buffer is finished. The interrupt generated
after the first buffer finishes in this case is useless to software, because the interrupt
handling routine is not able to get access to the Am5
x
86 CPU bus (because the GP-DMA
controller is programmed for block transfer mode).
Note that the GPDRQx signal must be deasserted before an active channel can be masked.
14.5.10 Latency
14.5.10.1 Nonpreemptive Latency
The ÉlanSC520 microcontroller implements a write buffer and a read buffer (with read-
ahead feature) to optimize SDRAM performance. These buffers can improve GP-DMA
latency during block transfer or demand transfer.
■
During a write transfer, the write buffer collects bytes (or words) from the GP bus and
writes back to SDRAM in a full doubleword. This mechanism effectively provides one-
wait-state write accesses to SDRAM, as seen from the GP-DMA controller.
■ During a read transfer, the read buffer reads the entire cache-line (16 bytes). This
effectively provides zero-wait-state read accesses from SDRAM by the GP-DMA
controller. However, since the read buffer fetches forward, GP-DMA channels that are
configured in address decrement mode experience more read buffer misses. The read
buffer does not prefetch for GP-DMA accesses because they are less than one
doubleword.