AMD Elan SC520, User Manual, Page: 388 / 444

Boundary Scan Test Interface
25-2 Élan™SC520 Microcontroller User’s Manual
25.3 REGISTERS
The ÉlanSC520 microcontroller contains four test data registers: Bypass register, Boundary
Scan register, Device Identification register and Serial Debug Port Data register. A fifth
register, the Instruction register, is used to specify the test to be executed and the data
register to be accessed.
The Bypass register and Boundary Scan register are serially connected to JTAG_TDI and
JTAG_TDO, with JTAG_TDI connected to the most significant bit and JTAG_TDO
connected to the least significant bit of the test data register. Data is shifted one stage (bit
position within the register) on each rising edge of the test clock (JTAG_TCK). Table 25-1
gives a description of each register. The Serial Debug Port Data register is part of the
AMDebug utility and is physically located in the AMDebug logic. See Chapter 26,
“AMDebug™ Technology”, for more information on the AMDebug interface.
25.4 OPERATION
The test and debugging features on the ÉlanSC520 microcontroller include the following
elements:
■
Pins—JTAG_TDI, JTAG_TMS, JTAG_TDO, JTAG_TCK and JTAG_TRST. In addition,
there are four pins for the AMDebug utility: CMDACK, BR/TC, STOP/TX, and TRIG/
TRACE.
■ Instruction Register (IR)—The instruction codes select the specific test or debug
operation to be performed and the test data register to be accessed.
■ Test Data Registers—Boundary Scan (BSR) register, Device Identification (DID)
register, Bypass (BPR) register, and Serial Debug Port Data (SDPD) register.
■ Test Access Port (TAP) controller—State-machine and control logic implementation.
The instruction and test data registers are separate shift-register paths connected in parallel
that have a common serial data input and a common serial data output connected to the
TAP signals, JTAG_TDI and JTAG_TDO, respectively.
Table 25-1 Chip Test and Debugging Registers
Register Mnemonic Function
Boundary Scan BSR A single shift register path containing the boundary scan cells that are
connected to all input and output pins of the ÉlanSC520 microcontroller.
Figure 25-1 shows the logical structure of the Boundary Scan register. Data
is transferred without inversion from JTAG_TDI to JTAG_TDO through the
Boundary Scan register during scanning. The Boundary Scan register is
affected by the EXTEST and SAMPLE/PRELOAD instructions.
Bypass BPR Provides a path from JTAG_TDI to JTAG_TDO with one clock cycle
latency.Used to bypass the chip completely while testing boards containing
many chips.
Device Identification DID A 32-bit register that contains AMD’s ID code for the ÉlanSC520
microcontroller.
Serial Debug Port Data SDPD A 38 bit register that serves as a command/status/data interface with the
Am5
x
86 CPU processor. Figure 25-2 on page 25-13 shows the format.
Instruction IR Determines the test that has to be executed and the data register to access.