AMD Elan SC520, User Manual, Page: 140 / 444

System Arbitration
8-16 Élan™SC520 Microcontroller User’s Manual
■
Clock #3: The PCI bus arbiter samples REQ asserted and begins arbitration. Master 0
has higher priority at this time than master 1 so the PCI bus arbiter grants the PCI bus
to master 0.
■ Clock #4: Master 0 samples the bus idle and its GNT0 signal asserted and begins a
transaction by asserting FRAME. Master 0 now becomes the lowest priority master in
the rotating priority queue.
■
Clock #5: The PCI bus arbiter detects a transaction has started and rearbitrates for the
next master. Master 1 is the now the highest priority master in the rotating priority queue,
so the PCI bus arbiter deasserts the GNT0 for master 0 and asserts the GNT1 for master
1.
■
Clock #8: Master 1 samples the bus idle and its GNT1 asserted and begins a transaction
by asserting FRAME. Master 1 now becomes the lowest priority master in the rotating
priority queue.
■ Clock #9: No other masters are requesting the bus, so the PCI bus arbiter keeps
asserting the GNT1 for master 1. This allows master 1 to continue the transaction, even
after its master latency timer has expired. If another master were requesting the bus,
the PCI bus arbiter would rearbitrate, deassert the GNT1 for master 1, and assert the
GNT for the next master to be granted the bus.
8.4.4.5 PCI Bus Arbitration Parking
Figure 8-10 shows an example of bus parking in concurrent arbitration mode when no
master is requesting access to the PCI bus.
In this example, the PCI bus arbiter is configured to park on the Am5
x
86 CPU. If the PCI
bus arbiter is configured to park on the last master that acquired the bus, then the PCI bus
arbiter would continue to assert the GNT to the master that had just completed a transaction.
Figure 8-10 PCI Bus Concurrent Mode Arbitration Parking
Notes:
In Figure 8-10, req/gnt are for the Am5
x
86 CPU.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLKPCIIN
REQ0
GNT0
req
gnt
FRAME
IRDY
TRDY