AMD Elan SC520, User Manual, Page: 368 / 444

Synchronous Serial Interface
22-8 Élan™SC520 Microcontroller User’s Manual
Figure 22-9 SSI Timing: TC_INT and BSY_STA Bits
22.5.6 Software Considerations
A slave should be enabled (if necessary) before a transmit or receive transaction is initiated
and disabled after the transaction is complete. Software is responsible for controlling PIOs
to implement chip enable signals, including setup and hold time specifications. These pins
do not have associated SSI hardware functionality. See Chapter 23, “Programmable Input/
Output”, for descriptions of these pins.
Unreliable operation will occur if the configuration is modified or a second SSI command
is written during an active operation. Writes to the SSI Transmit (SSIXMIT) register, SSI
Control (SSICTL) register, and SSI Command (SSICMD) register should not be performed
while the SSI is busy. Software should load the SSI Transmit (SSIXMIT) register (if
necessary) before writing an SSI command. The SSI Receive (SSIRCV) register (MMCR
offset CD4h) should not be read until a receive transaction is complete.
22.6 INITIALIZATION
The SSI port is disabled during system reset, and all SSI register bits are initialized to 0.
The SSI is enabled after reset, but inactive until an SSI command is executed. Some or all
of the following steps should be taken to initiate an SSI transaction.
1. Enable/disable CPU transaction complete interrupt via the TC_INT_ENB bit in the SSI
Control (SSICTL) register.
2. Enable/disable inverted phase mode via the PHS_INV_ENB bit in the SSI Control
(SSICTL) register (MMCR offset CD0h).
3. Enable/disable inverted clock mode via the CLK_INV_ENB bit in the SSI Control
(SSICTL) register.
4. Enable/disable MSBF mode via the MSBF_ENB bit in the SSI Control (SSICTL) register.
5. Select SSI clock speed via the CLK_SEL bits in the SSI Control (SSICTL) register.
6. Enable/disable device enable pins using PIOs.
7. Write output data to the SSI Transmit (SSIXMIT) register (MMCR offset CD1h).
8. Write an SSI command to the SSI Command (SSICMD) register (MMCR offset CD2h).
9. Wait for a transaction complete interrupt or poll the SSI Status (SSISTA) register (MMCR
offset CD3h) to read BSY bit for port activity status, if the interrupt is disabled.
10.Read input data from the SSI Receive (SSIRCV) register (MMCR offset CD4h).
11.Write a 1 to the TC_INT bit in the SSI Status (SSISTA) register to clear bit and
acknowledge the interrupt, if enabled.
SSI_CLK
SSI_CLK
PHS_INV_ENB=0
PHS_INV_ENB=1
BSY=0
TC_INT=1 BSY=1
TC_INT=0
Write 1 to TC_INT
BSY=0
TC_INT=1 BSY=1
TC_INT=0
Write 1 to TC_INT
Write SSI command
Write SSI command
BSY=0
TC_INT=1
TC_INT=0
Write 1 to TC_INT
CLK_INV_ENB=0
CLK_INV_ENB=1