AMD Elan SC520, User Manual, Page: 354 / 444

UART Serial Ports
21-8 Élan™SC520 Microcontroller User’s Manual
16550-compatible mode, the Overrun Error (OE) bit is set if a new character is
completely received into the shift register when the FIFO is already 100% full. Data
in the FIFO is not overwritten by this overrun. However, the data in the shift register
is lost.
21.5.3 Error Handling
Received data can contain three types of abnormal conditions in addition to the overrun
error:
■ Parity errors
■
Framing errors
■ Break indications
21.5.3.1 Parity Error
A parity error indicates that the parity bit for the character in error did not match the parity
indicated by the Even Parity Select (EPS) bit, Stick Parity Enable (SP) bit, and the
Asynchronous Data Parity Enable (PENB) bit in the UART x Line Control (UARTxLCR)
register.
21.5.3.2 Framing Error
A framing error indicates that the bit following the parity bit (if parity is enabled) or following
the last data bit (if parity is not enabled) was detected to be a logic 0. To resynchronize
following this type of error, the UART assumes that the framing error was due to the next
start bit occurring too early. It samples the start bit twice (once as the erroneous stop bit of
the first character and once as the start bit of the second character) before sampling the
data for the second bit.
21.5.3.3 Break Indication
A break indication means that the received data input was detected to be 0 for a time longer
than a full UART frame (including start bit, data bits, parity, and stop bits). The character
loaded into the FIFO on a break indication is always 0, and subsequent characters are
loaded normally once the receive input returns to its idle state (high).
21.5.3.4 Error Reporting
21.5.3.4.1 16450-Compatible UART Mode
In 16450-compatible mode, the error bits (OE, PE, FE, and BI) in the UART x Line Status
(UARTxLSR) register indicate that the error was detected during reception of the current
byte in the UART x Receive Buffer (UARTxRBR) register. If receiver line status Interrupts
are enabled, any of the OE, PE, FE, or BI conditions trigger an interrupt.
21.5.3.4.2 16550-Compatible UART Mode
In 16550-compatible mode, the error bits (PE, FE, and BI) are set only when an error
condition is detected in the character at the top of the FIFO. Since reading the UART x
Receive Buffer (UARTxRBR) register causes the FIFO to advance to the next received
character, the error bits must be read from the UART x Line Status (UARTxLSR) register
prior to the data being read from the FIFO. The ERR_IN_FIFO bit in the UART x Line Status
(UARTxLSR) register can be used to detect if
any of the characters in the FIFO (not just
the one at the top) had errors.
All of the error bits, with the exception of the ERR_IN_FIFO bit, are cleared when the UART
x Line Status (UARTxLSR) register is read. The ERR_IN_FIFO bit is cleared when the
UART x Line Status (UARTxLSR) register is read and all data present in the FIFO is error-
free, or the FIFO becomes empty.