AMD Elan SC520, User Manual, Page: 278 / 444

GP Bus DMA Controller
14-12 Élan™SC520 Microcontroller User’s Manual
14.5.3.2 Addressing In Enhanced GP-DMA Mode
In enhanced GP-DMA mode, channels 3, 5, 6 and 7 are programmable to support either
8-bit transfers or 16-bit transfers.
■ When the channel is configured to be 8-bit, the address is generated as shown in
Table 14-6.
■ When the channel is configured to be 16-bit, the address is generated as shown in
Table 14-7.
■ However, when the buffer chaining feature is used, the memory address of the next data
buffer is provided directly from the channel’s Next Address register. This feature is
described in “Buffer Chaining” on page 14-15.
The size of the address adder is increased to 28 bits wide to eliminate the limitation of
64-Kbyte physical page boundaries for 8-bit transfers and 128-Kbyte physical page
boundaries for 16-bit transfers. This feature is available for channels 3, 5, 6, and 7 only.
14.5.4 GP-DMA Transfer Modes
The GP-DMA controller performs read, write, and verify operations in each of the three
transfer modes: single, demand, or block. For all three modes, the GP-DMA initiator asserts
GPDRQx and must hold it active until the assertion of GPDACKx in order to be recognized.
14.5.4.1 Single Transfer Mode
In single transfer mode, the GP-DMA controller performs one transfer each time it is granted
the Am5
x
86 CPU bus. The GP-DMA initiator asserts GPDRQx and holds it active as long
as it has data to be transferred. The initiator must negate its DRQx relative to the I/O
commands to ensure correct operation.
14.5.4.2 Demand Transfer Mode
In demand transfer mode, the GP-DMA initiator asserts GPDRQx and holds it active as
long as it has data to be transferred. The GP-DMA controller continues to perform GP-DMA
transfers until Terminal Count (TC) is reached or the GPDRQx is deasserted by the GP-
DMA initiator. The initiator must negate its DRQx relative to the I/O commands to ensure
correct operation.
When using demand transfer mode, if the transfer is configured for automatic initialization
control mode, GPDRQx must be deasserted prior to the assertion of GPTC in the last DMA
cycle to prevent another transfer. Otherwise, the channel is automatically masked and
requires initialization before it will respond to subsequent requests.
Table 14-6 8-Bit GP-DMA Channel Address Generation
Source
GP-DMA Channel x
Extended Page Registers
Slave DMA Channel x
Page Registers
Slave DMA Channel x
Memory Address Register
Address A27–A24 A23–A16 A15–A0
Table 14-7 16-Bit GP-DMA Channel Address Generation
Source
GP-DMA Channel x
Extended Page Registers Master DMA Channel x
Page Registers Master DMA Channel x
Memory Address Register
Address A27–A24 A23–A17 A16–A1, A0=0