AMD Elan SC520, User Manual, Page: 281 / 444

GP Bus DMA Controller
Élan™SC520 Microcontroller User’s Manual 14-15
14.5.4.6 Priority
The GP-DMA controller offers two priority schemes for servicing multiple requests. After
the recognition of any one channel for service, the other channels are prevented from
generating DMA cycles until the current transfer has completed (i.e., the current channel’s
DACKx has deasserted).
■ The fixed priority scheme is based upon the value of channel numbers (Channel 0 is
the highest priority, Channel 7 is the lowest priority). The higher priority channel prevents
the lower priority channel from servicing the request.
■
In the rotating priority scheme, the last channel serviced becomes the lowest priority,
with the other channels rotating accordingly. This scheme is also known as the round
robin scheme.
14.5.4.7 Buffer Chaining
In enhanced GP-DMA mode, channels 3, 5, 6, and 7 allow transfer to/from two or more
data buffers in SDRAM for a single transfer request (fragmented data buffers). This feature
is known as
buffer chaining. The purpose of this feature is to facilitate GP-DMA transfers
to or from non-contiguous buffers in SDRAM.
An example usage of this feature is to transfer a packet of data from SDRAM to the external
device. The packet header and the packet data might be in two noncontiguous locations
in SDRAM. By using the buffer chaining feature, users can transfer both the packet header
and packet data in one DMA transfer. Similarly, the GP-DMA controller can be used to split
up a packet header from the packet data into two SDRAM buffers when receiving packets.
Buffer chaining mode is enabled by setting the appropriate CHx_BCHN_ENB bit in the
Buffer Chaining Control (GPDMABCCTL) register (MMCR offset D98h).
1. The Next Address registers and the Next Transfer Count registers should be
programmed prior to the start of the GP-DMA cycle.
2. When the transfer count is reached, the GP-DMA controller checks the CHx_CBUF_VAL
bits in the Buffer Chaining Valid (GPDMABCVAL) register (MMCR offset D9Bh).
3. If this bit is set, the contents of the Next Address and the Next Transfer Count registers
are loaded into the internal current address and current transfer count registers,
respectively.
4. The GP-DMA controller hardware then generates a maskable or non-maskable interrupt
and clears the CHx_CBUF_VAL bits.
5. This bit indicates to software that another buffer can be set up in the chain by writing to
the Next Address and Next Transfer Count registers with new values.
6. The DMA transfer then continues until the next terminal count.
7. If the CHx_CBUF_VAL bits were not set, GP-DMA controller generates the interrupt and
also asserts GPTC to indicate the end of the chain.
Typically, buffer chaining should be used in single transfer mode, but block mode or demand
mode operation is also supported.
When using block transfer mode, the GP-DMA controller holds the bus request active until
the end of the last buffer in the chain. It is worth noting that only two buffers can be chained
at a time when using block transfer mode. Because the GP-DMA controller does not release
the GP bus during the transfer, the Next Address and Next Transfer Count cannot be
reprogrammed to link in another buffer while a GP-DMA transfer is in progress.