AMD Elan SC520, User Manual, Page: 76 / 444

System Initialization
3-20 Élan™SC520 Microcontroller User’s Manual
3.8.3 Interrupt Polarity
Each of the interrupt controllers can recognize either a Low-to-High edge-triggered or an
active High level-sensitive interrupt request. To support external devices that generate
active Low interrupt requests (either edge or level), a programmable inversion of each of
the external interrupt requests is available.
Many devices generate a Low-going interrupt signal using an open-collector output. These
devices are easily supported on the ÉlanSC520 microcontroller by setting the appropriate
bit in the Interrupt Pin Polarity (INTPINPOL) register (MMCR offset D10h). For example, if
such a device were connected to GPIRQ8, then setting GPINT8_POL in the Interrupt Pin
Polarity (INTPINPOL) register would program the interrupt for a Low-going interrupt input.
It is important to ensure that the polarity values for all internal interrupt sources are
programmed correctly at reset time.
3.9 CONFIGURING THE PROGRAMMABLE I/O PINS
An important part of the ÉlanSC520 microcontroller initialization is configuration of the
programmable I/O (PIO) pins. These are general-purpose I/O pins that can be programmed
as inputs or outputs. When configured as an input, the state of the input can be read using
the PIOx_DATA bit in the PIOx Data register.
The PIO pins can also be configured as outputs by setting their corresponding direction
bits in the PIOx Direction registers.
3.10 CONFIGURING THE PCI HOST BRIDGE AND ARBITRATION
The PCI Host Bridge must be configured and initialized before PCI operation such as
enumeration and device configuration take place. There are two parts to the PCI host bridge
configuration: ÉlanSC520 microcontroller-specific configuration and normal PCI bus
configuration.
1. Configure the PCI host bridge.
a. Program the desired ÉlanSC520 microcontroller arbitration mode, including
concurrency mode and PCI bus master arbitration priorities, etc. See “Initialization”
on page 8-22, for more detailed information on arbitration.
b. Program the Programmable Address Region (PAR) registers, if required. If there are
one or two VGA video controllers, PAR 0 and PAR 1 may need to be programmed to
place the VGA graphics memory in SDRAM space at PC-compatible locations. PAR
0 and PAR 1 could also be used for other PCI peripherals (such as a network card)
that require mapping below physical address 00100000h. See Chapter 4, “System
Address Mapping”, for details on programming PCI bus memory space.
c. Program the ÉlanSC520 microcontroller-specific PCI host bridge configuration (write
posting, retry time-out counter, interrupts, etc.). Note that write-posting must be
disabled while operating in nonconcurrent arbitration mode. See Chapter 8, “System
Arbitration”, for further details on nonconcurrent mode arbitration.
d. Program the standard PCI bus configuration registers. See “Configuration Information”
on page 9-9 for more information.
2. Configure the external PCI bus devices.
In general, PCI host bridge configuration bits should not be changed except during a PCI
bus initialization after a system or programmable reset.