AMD Elan SC520, User Manual, Page: 127 / 444

System Arbitration
Élan™SC520 Microcontroller User’s Manual 8-3
8.4 OPERATION
The ÉlanSC520 microcontroller’s arbitration subsystem consists of two separate bus
arbitration units for the CPU bus and the PCI bus.
■ The CPU bus arbiter arbitrates between the Am5
x
86 CPU, the PCI host bridge, and the
GP-DMA controller on the internal CPU bus.
■ The PCI bus arbiter arbitrates between the Am5
x
86 CPU and up to five external PCI
masters on the external PCI bus.
8.4.1 Operating Modes
The system arbiter can operate in two modes for maximum flexibility:
■ Nonconcurrent arbitration mode
■
Concurrent arbitration mode
The two bus arbiters operate completely independently when the system is configured for
concurrent arbitration mode, but they are interlocked when the system is configured for
nonconcurrent arbitration mode.
Maximum performance is typically achieved in concurrent arbitration mode, because this
allows simultaneous PCI bus and CPU bus operation. However, some systems may benefit
from nonconcurrent arbitration mode, especially if the system experiences data coherency
problems due to older, non-compliant bus bridges.
The arbitration mode is specified with the CNCR_MODE_ENB bit in the System Arbiter
Control (SYSARBCTL) register (MMCR offset 70h). System arbitration defaults to
nonconcurrent arbitration mode after reset.
8.4.1.1 Nonconcurrent Arbitration Mode
Nonconcurrent arbitration mode forces all masters to automatically acquire ownership of
both PCI and CPU buses, regardless of destination of the cycles. In this mode, no
concurrency between the CPU bus and the PCI bus is allowed. External PCI masters are
only granted the PCI bus when the host bridge has been granted the CPU bus, even for
peer-to-peer transfers.
When an external PCI bus master requests the PCI bus, the following occurs:
1. The PCI bus arbiter samples an external PCI request asserted and asserts the host
bridge request to the CPU bus arbiter. The PCI bus arbiter is parked on the CPU by
default and should not be programmed to park on the last master in this mode.
2. The CPU bus arbiter samples the host bridge request asserted and grants the CPU bus
to the host bridge at the completion of the next Am5
x
86 CPU cycle. The CPU bus is
owned by the Am5
x
86 CPU by default, so a request to the CPU must be asserted to
gain ownership of this bus.
PCI Host Bridge Interrupt
Mapping PCIHOSTMAP D14h System arbiter and PCI host bridge interrupt
mapping to any of 22 available interrupt
channels or NMI, PCI NMI enable control
Table 8-1 System Arbitration Registers—Memory-Mapped (Continued)
Register Mnemonic
MMCR
Offset
Address
Function