AMD Elan SC520, User Manual, Page: 305 / 444

Programmable Interrupt Controller
Élan™SC520 Microcontroller User’s Manual 15-17
identifies which IR inputs are hooked up to slave controllers. For the slave controllers,
it identifies the IR pin on the master to which that particular slave is connected.
It is important to note that the ÉlanSC520 microcontroller’s PIC can be configured as a
stand-alone master controller, one slave cascade (either Slave 1 or Slave 2), or cascading
with both slave controllers.
– To configure it as a stand-alone Master controller where 8 or fewer interrupt requests
are available to the user, bits 2 and 5 must be cleared to 0 in the Master PIC Initialization
Control Word 3 (MPICICW3) register (Port 0021h).
– To configure it as a Slave 1 only cascade, the S2 and S5 bits must be set and cleared
respectively in the Master PIC Initialization Control Word 3 (MPICICW3) register (Port
0021h).
– For Slave 2 cascade only configuration, the S2 and S5 bits must be cleared and set
respectively in the Master PIC Initialization Control Word 3 (MPICICW3) register (Port
0021h).
– To configure cascading using both the slave controllers, the S2 and S5 bits must be
set in the Master PIC Initialization Control Word 3 (MPICICW3) register (Port 0021h).
4. Finally, the Initialization Control Word 4 (xICW4) register (written only if indicated in the
Initialization Control Word 1 (xICW1) register) controls whether EOIs are generated
manually or automatically. It also contains some bits that must always be set in the
ÉlanSC520 microcontroller.
Note that some parameters in the PIC configuration registers are fixed based on the way
the controllers are arranged in the ÉlanSC520 microcontroller.
For example, the Slave 1 PIC Initialization Control Word 3 (S1PICICW3) register (Port
00A1h) always contains 2d to indicate that Slave 1 is hooked up to IR2 on the Master
controller.
For those configuration parameters that are not fixed, software that initializes the controllers
must be very careful to accurately reflect the correct arrangements of the controllers, as
shown in Figure 15-1 on page 15-3.
For example, if neither Slave controller is being bypassed, the Master PIC Initialization
Control Word 3 (MPICICW3) register (Port 0021h) should contain 24h (or 00100100b) to
indicate that slave controllers are hooked up to its IR2 and IR5 signals.
After the interrupt controllers are initialized, any subsequent reads or writes to ports 021h,
0A1h, or 025h access the Interrupt Mask (xINTMSK) register of the Master, Slave 1, or
Slave 2 controllers. The Operation Control Word 2 (xOCW2) and Operation Control Word
3 (xOCW3) registers are accessed by writing to the appropriate ports, 020h, 0A0h, or 024h.
The controllers can be configured in various modes using these registers.
5. Initializing the Interrupt Mask (xINTMSK) register provides the masking of the interrupt
requests on a per channel basis.
6. Writing to the Operation Control Word 2 (xOCW2) register configures the various rotation
and EOI modes.
7. Finally, the Operation Control Word 3 (xOCW3) register configures the different mask
modes, controls reading of the In-Service (xISR) register or the Interrupt Request (xIR)
register, and whether the controller is to be used by software to perform polling.
The rest of the non-controller specific registers are programmed next. This includes
programming the routing of the various interrupt sources to the appropriate priority level or