AMD Elan SC520, User Manual, Page: 135 / 444

System Arbitration
Élan™SC520 Microcontroller User’s Manual 8-11
8.4.4 Bus Cycles
This section includes example timing diagrams showing various types of arbitration that
may occur in the ÉlanSC520 microcontroller. Note that these are example cases only, and
not all cases are shown. The diagrams are functionally representative in nature, and should
not be used to infer detailed timing information. Note also that the synchronization between
the CPU and PCI clock domains is not shown in detail.
8.4.4.1 CPU Bus Arbitration
Figure 8-6 shows CPU bus arbitration between two CPU bus masters (for clarity, this
diagram shows only two bus masters). For additional CPU bus masters, there would be
more arbitration signal groups and more than one CPU bus transaction could take place
before an individual CPU bus master would be granted the bus.
Figure 8-6 CPU Bus Arbitration
Notes:
In Figure 8-6, the CPU bus master signals are labeled mst_xxx and the Am5
x
86 CPU signals are labeled cpu_xxx.
Snooping is not shown in this figure.
The clk signal denotes the 33-MHz clock source and represents both the CPU clock and the PCI clock. This diagram
does not represent the full synchronization of signals between these clock domains.
The following sequence annotates the CPU bus arbitration cycle shown in Figure 8-6.
■ Clock #1: The Am5
x
86 CPU requests the bus by asserting cpu_breq. Note at this time
that the bus is granted to some other master because cpu_hlda is asserted.
■ Clock #2: The CPU bus arbiter samples the Am5
x
86 CPU’s request asserted and begins
arbitration. The CPU bus arbiter determines that the bus is free and that the Am5
x
86
CPU is the next master to receive the bus, so it deasserts cpu_hold to the Am5
x
86 CPU.
If the bus was not free or the Am5
x
86 CPU was not the next master to receive the bus,
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
clk
cpu_breq
cpu_hold
cpu_hlda
cpu_ads
cpu_rdy
mst_req
mst_gnt
mst_ads
mst_rdy