AMD Elan SC520, User Manual, Page: 227 / 444

Write Buffer and Read Buffer
Élan™SC520 Microcontroller User’s Manual 11-13
Large PCI burst requests will benefit more from the read-ahead function than short, frequent
independent PCI read transfers. Since the Am5
x
86 CPU is a major requestor of SDRAM
read accesses, short and frequent independent PCI transfers may result in read-ahead
thrashing. For example, data prefetched for Am5
x
86 CPU read requests may possibly not
be used by PCI read requests and data prefetched for the PCI request may possibly not
be used by the Am5
x
86 CPU.
11.5.5 Software Considerations
The write buffer and read buffer require minimal configuration overhead.
Data coherency is maintained in hardware during write buffer configuration changes. This
implies that when the write buffer is disabled, the contents are automatically flushed to
SDRAM as a high priority, prior to allowing any master activity to occur to SDRAM. Even
though a write buffer flush occurs automatically when it is disabled, a manual write buffer
flush control is provided for software control via the WB_FLUSH bit in the SDRAM Buffer
Control (DBCTL) register (MMCR offset 40h). If the read-ahead feature is disabled, the
prefetched data remains in the read buffer.
Both the write buffer and read-ahead feature of the read buffer are disabled after a system
reset or programmable reset. It is recommended that the write buffer be disabled prior to
SDRAM sizing, SDRAM test, or other software activity that must have guaranteed write
data delivery to the physical SDRAM array prior to reading. Failure to disable the write
buffer for these usages may result in false SDRAM sizing or test indications.
Typically during SDRAM sizing or test, SDRAM is written and then read back to determine
either if SDRAM exists at that location (during sizing) or if SDRAM is functional at that
location (during test). Since the write buffer provides a read-merging function to reduce the
overhead associated with maintaining data coherency, data is
not forced from the write
buffer to SDRAM prior to the read-back of the data. (This overhead would normally be
required for
non-snooping write buffers that do not support read-merging to maintain
coherency.) Should the read occur while the associated write data is still in the write buffer,
the correct data is read-merged with data from SDRAM, thus providing the correct read
data even though the write data was not yet written to SDRAM. If, in this scenario, SDRAM
was non-existent, it would appear as though it did exist, thus resulting in either an invalid
SDRAM size or false “pass” status during a SDRAM test algorithm. If the write data migrated
to SDRAM
before the read-back, a correct indication would result.
The write buffer must be disabled only in these scenarios where software requires
guaranteed delivery of write data to SDRAM prior to testing. Under normal program
execution, the write buffer and read buffer “appear” as the SDRAM storage array.
11.5.6 SDRAM Bandwidth Improvements
When enabled, the performance benefit that the write buffer offers is its ability to effectively
decouple the master write activity from incurring the SDRAM latency penalty. This in effect
leaves the SDRAM free to satisfy a higher demand in read activity by all masters. To further
optimize this, when the write buffer is enabled, it allows master read requests to occur
around write data posted in the write buffer. In effect, read cycles are given priority to SDRAM
when the write buffer is enabled. However, there are conditions that give the write buffer
write priority to SDRAM over reads. These are:
■ Flush priority is given to the write buffer when the write buffer configuration changes to
disabled.
■ The user exercises the manual write buffer flush feature.