AMD Elan SC520, User Manual, Page: 243 / 444

ROM/Flash Controller
Élan™SC520 Microcontroller User’s Manual 12-13
is an easy restriction to overcome, because programming Flash is usually done during non-
performance critical periods, such as during user configuration. However, new “dual boot”
Flash allows fetching instructions from one portion of the device while programming or
erasing a sector in another portion.
Typically, Flash is programmed (or erased) by writing a program command sequence to an
address within the sector to be modified, followed by the erase command or the target
address and data.
An example program command sequence is:
1. Write the byte AAh to address 555h within the sector.
2. Write the byte 55h to address 2AAh within the sector.
3. Write the byte A0h to address 555h within the sector.
4. Write the actual data to the actual address. If the base of a 1-MByte boot device is at
0FFF00000h, then a programming sequence for the first sector would start at address
0FFF00555h.
The actual values and addresses used vary by device.
After issuing the command, the programming code must wait until the embedded algorithm
is complete before sending further programming requests to the Flash device. There are
several ways to determine this.
■
One way is to poll the status of a ready/busy hardware pin (which would be connected
to a PIO pin).
■
The second way is to continually read the address that was programmed, looking for
one of several indications that the event is complete.
A typical waiting period is 16 ms. Sector erase can take from 1 s to up to 10 s near the end
of the serviceable life of the device.
Both the program command sequence and the status read have implications for the use
of the ÉlanSC520 microcontroller in Flash programming applications.
First, the area being programmed must set to be noncacheable. Writing the program
command sequence does not actually change the physical addresses involved, meaning
that caching this area would yield incorrect data the next time it is read. Also, the status
read phase relies on the value of externally supplied bits to change from one read to another.
Obviously, satisfying such a read from the cache would not work. Once the programming
is complete, it is legitimate and desirable to enable caching on this region.
Another obvious implication is that programming Flash device requires a write strobe to be
connected to the device. Devices are programmed in their natural word length, meaning
that byte write enables are not required. During writes, there are minimum times for the
write strobe pulse width. These follow naturally from the total chip enable cycle time, which
would be used to determine the number of wait states to use when accessing the device
for reads, requiring no special timing modifications. Flash requires a minimum reset pulse
width of 500 ns, which is well within the ÉlanSC520 microcontroller’s minimum time.
12.5.5 Latency
ROM latency refers to the amount of time in which a ROM access can impact system
performance. For example, during an Am5
x
86 CPU access to ROM, no other master in the
system will be granted access to the SDRAM resource. The latency time will be mainly
affected by the width and the access time of the ROM device.