AMD Elan SC520, User Manual, Page: 121 / 444

Am5
x
86
®
CPU
Élan™SC520 Microcontroller User’s Manual 7-3
7.4 OPERATION
The ÉlanSC520 microcontroller is a highly integrated system in silicon, and the Am5
x
86
CPU is central to this integration. The Am5
x
86 CPU is a high-performance CPU that is fully
software-compatible with the Am486 microprocessor family. Most of the details of the
communication between the Am5
x
86 CPU core and the peripherals are transparent to the
user and are not documented here.
A full description of the operation of the Am5
x
86 CPU is well beyond the scope of this
chapter. The following AMD publications are a good starting point for learning about the
Am5
x
86 CPU as it has evolved over time. The oldest publication is listed first. The later
publications enhance the original functional descriptions.
■
Am486
®
DX/DX2 Microprocessor Hardware Reference Manual, 1994 (order #17965)
■ Enhanced Am486
®
Microprocessor Family Data Sheet, 1995, (order #19225)
■
Am5
x
86® Microprocessor Family Data Sheet, 1996 (order #19751)
The Am5
x
86 CPU core in the ÉlanSC520 microcontroller is derived from the Enhanced
Am486 family (as described in order #19225). The Am5
x
86 CPU enhances system
performance by raising the maximum CPU operating frequency to 133 MHz, while
maintaining complete compatibility with the standard Am486 CPU architecture. The
following differences may be relevant to the user:
■ There is no provision for an L2 cache. The signals that would be needed are not brought
out of the ÉlanSC520 microcontroller.
■ System management mode (SMM) is not supported on the ÉlanSC520 microcontroller.
■
From an Am5
x
86 CPU-core perspective only, the cache defaults to the write-back cache
mode and reports this state in response to the CPUID instruction. The cache mode can
be reconfigured to write-through mode via the Am5
x
86 CPU Control (CPUCTL) register
(MMCR offset 02h).
Programs sometimes require the ability to determine the hardware on which they are
running. The ÉlanSC520 microcontroller can be identified via the CPUID instruction and
the ÉlanSC520 Microcontroller Revision ID (REVID) register (MMCR offset 00h). This is
discussed in “Identifying the CPU Core” on page 3-7.
7.4.1 Floating Point Unit (FPU)
The Am5
x
86 CPU provides an integrated floating point unit (FPU) that operates in parallel
with the Arithmetic Logic Unit (ALU). The FPU is useful in applications that involve more
intensive computational complexity. The major features of the integrated FPU are:
■
Compliant with ANSI/IEEE 754 standard
■
Provides arithmetic instructions to handle various numeric data types and formats
■ Provides built-in transcendental functions for functions like sine, cosine, tangent,
logarithms, etc.
■ Software-compatible with the 80387 (and previous) math co-processors