AMD Elan SC520, User Manual, Page: 134 / 444

System Arbitration
8-10 Élan™SC520 Microcontroller User’s Manual
8.4.3.2 Bus Parking
The PCI bus arbiter parks the bus on a PCI bus master when the bus is idle (no master is
requesting the bus). This is required on the PCI bus to guarantee that the bus is properly
terminated at all times. The PCI bus arbiter arbitrates for the next transaction as soon as
the current PCI master that is granted the bus begins its transaction.
Bus parking is configured with the BUS_PARK_SEL bit in the System Arbiter Control
(SYSARBCTL) register (MMCR offset 70h). Note that the BUS_PARK_SEL bit must not
be changed except during PCI bus arbiter initialization after a system of programmable
reset.
8.4.3.2.1 Nonconcurrent Arbitration Mode Bus Parking
The bus should always be parked on the CPU in nonconcurrent arbitration mode. This is
necessary to guarantee adequate CPU performance. Otherwise, the CPU would be
required to acquire ownership of both the CPU bus and the PCI bus for each external
access (including code fetches).
8.4.3.2.2 Concurrent Arbitration Mode Bus Parking
In concurrent arbitration mode, the PCI bus arbiter can be configured to park on the last
master that was granted the bus or configured to always park on the Am5
x
86 CPU. If no
other PCI masters are requesting the bus, the GNT to the current PCI master remains
asserted until the current PCI master transaction completes.
A bus master that is parked can start a transaction without asserting its REQ pin (PCI bus
protocol allows a master to start a cycle when its GNT is asserted and the bus is idle), but
it must assert REQ if it requires multiple transactions.
When no PCI bus requests or grants are active, the arbiter retains priority established from
the last tenure. For example, if the bus is idle and no requests or grants are active and all
masters simultaneously request the bus, the arbiter services the master that is next in
rotation.
8.4.3.3 Rearbitration
A PCI bus master that is granted the bus and has not started a transaction within 16 clocks
after the bus becomes idle can be assumed to be “broken.” In this case, the PCI bus arbiter
automatically re-arbitrates and grants the bus to the next PCI master.
An interrupt can be generated when a PCI bus master that has acquired bus ownership
has not started a transaction within 16 clocks, and the REQ/GNT number of the “broken”
PCI master is reported in the PCI Bus Arbiter Status (PCIARBSTA) register (MMCR offset
71h). This allows software to disable the broken master and modify the bus parking such
that the PCI bus is parked on the CPU.