AMD Elan SC520, User Manual, Page: 390 / 444

Boundary Scan Test Interface
25-4 Élan™SC520 Microcontroller User’s Manual
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When the TAP controller is in the Update-DR state, the SAMPLE/PRELOAD instruction
preloads data to the device pins to be driven to the board by executing the EXTEST
instruction. Data is preloaded to the pins from the Boundary Scan register on the falling
edge of JTAG_TCK.
25.4.1.1.3 IDCODE Instruction
The instruction code is 0010b. The IDCODE instruction selects the Device Identification
register to be connected to JTAG_TDI and JTAG_TDO, allowing the device identification
code to be shifted out of the device on JTAG_TDO. Note that the Device Identification
register is not altered by data being shifted in on JTAG_TDI.
25.4.1.1.4 HIGHZ Instruction
The instruction code is 0011b. The HIGHZ instruction connects the Bypass register between
JTAG_TDI and JTAG_TDO. This instruction forces all outputs to a high-impedance state.
25.4.1.1.5 BYPASS Instruction
The instruction code is 1111b. The BYPASS instruction selects the Bypass register to be
connected to JTAG_TDI or JTAG_TDO, effectively bypassing the test logic on the
ÉlanSC520 microcontroller by reducing the shift length of the device to one bit.
Note that an open circuit fault in the board-level test data path causes the Bypass register
to be selected following an instruction scan cycle due to the pullup resistor on the JTAG_TDI
input. This has been done to prevent any unwanted interference with the proper operation
of the system logic. The Instruction register can be accessed when this command is being
executed, because only the Boundary Scan register is affected during this instruction.
25.4.1.1.6 DEBUG Instruction
The instruction code is 0101. The DEBUG instruction enables a 38-bit dedicated data
register that serves as a command/status/data interface with Am5
x
86 CPU processor.
When the DEBUG instruction is written into the Instruction register, the serial debug shifter
is connected to the JTAG TDI–TDO serial interface. The DEBUG command and data are
loaded into and read from the serial debug shifter using the Capture-DR–Update-DR
sequence in the TAP controller state machine.
Loading the DEBUG instruction enables additional AMDebug technology signals to provide
pinpoint accuracy of external breakpoint assertion and elimination of status polling of the
JTAG serial interface. These signals are: CMDACK, BR/TC, STOP/TX and TRIG/TRACE.
25.4.2 Configuration Information
There are five scan paths from JTAG_TDI to JTAG_TDO in the ÉlanSC520 microcontroller:
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Instruction path
■ Bypass path
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Main data path through the Boundary Scan register
■ Serial Debug Port Data register
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Device Identification register
25.4.2.1 Instruction Path
This four-cell path is used to scan into the Instruction register. This chain is loaded when
the TAP controller is driven to the states Select-IR-Scan through Update-IR. See
Figure 25-4 on page 25-15.