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AMD Elan SC520 User Manual Download Page 124

Am5

x

86

®

 CPU

7-6

Élan™SC520 Microcontroller User’s Manual

bits in the Am5

x

86 CPU’s machine status (CR0) register, and the Am5

x

86 CPU’s write 

buffers retain the values they had prior to the soft reset.

A soft reset event clears the NMI_ENB bit in the Interrupt Control (PICICR) register, 
disabling NMIs. This allows software to initialize the stack pointer before setting the 
NMI_ENB bit again after a soft reset. 

Summary of Contents for Elan SC520

Page 1: ...lan SC520 Microcontroller User s Manual Order 22004A...

Page 2: ...ness for a particular purpose or infringement of any intellectual property right AMD s products are not designed intended authorized or warranted for use as components in systems intended for surgical...

Page 3: ...s access the AMD home page at www amd com and follow the Embedded Processors link These pages provide information on upcoming product releases overviews of existing products information on product sup...

Page 4: ...iv lan SC520 Microcontroller User s Manual...

Page 5: ...Interface 1 6 1 3 8 Clock Generation 1 6 1 3 9 Integrated Peripherals 1 7 1 3 10 JTAG Boundary Scan Test Interface 1 7 1 3 11 System Testing and Debugging Features 1 8 1 4 Applications 1 8 1 4 1 Smart...

Page 6: ...rupt Mapping 3 19 3 8 3 Interrupt Polarity 3 20 3 9 Configuring the Programmable I O Pins 3 20 3 10 Configuring the PCI Host Bridge and Arbitration 3 20 3 11 Disabling Internal Peripherals 3 21 CHAPTE...

Page 7: ...ogrammable Interval Timer 5 8 5 5 1 8 General Purpose Timers 5 8 5 5 1 9 Software Timer 5 8 5 5 1 10 Watchdog Timer 5 8 5 5 1 11 Real Time Clock 5 8 5 5 1 12 UART Serial Ports 5 8 5 5 1 13 Synchronous...

Page 8: ...on During Clock Speed Changes 8 7 8 4 3 PCI Bus Arbiter 8 7 8 4 3 1 PCI Bus Arbitration Protocol 8 8 8 4 3 2 Bus Parking 8 10 8 4 3 3 Rearbitration 8 10 8 4 4 Bus Cycles 8 11 8 4 4 1 CPU Bus Arbitrati...

Page 9: ...9 5 5 Interrupts 9 27 9 5 6 Latency 9 28 9 5 6 1 Master Latency 9 28 9 5 6 2 Target Latency 9 28 9 6 Initialization 9 29 CHAPTER 10 SDRAM CONTROLLER 10 1 10 1 Overview 10 1 10 2 Block Diagram 10 1 10...

Page 10: ...HAPTER 11 WRITE BUFFER AND READ BUFFER 11 1 11 1 Overview 11 1 11 2 Block Diagram 11 2 11 3 System Design 11 3 11 4 Registers 11 4 11 5 Operation 11 4 11 5 1 Write Buffer 11 5 11 5 1 1 Write Buffer Di...

Page 11: ...Chip Select Qualification 13 9 13 5 4 Data Sizing and Unaligned Accesses 13 9 13 5 5 Sharing the Address and Data Bus with the ROM Flash Controller 13 10 13 5 6 GP Bus Echo Mode 13 10 13 5 7 DMA Inte...

Page 12: ...14 15 14 5 4 7 Buffer Chaining 14 15 14 5 5 Bus Cycles 14 16 14 5 5 1 GP Bus I O to SDRAM 14 16 14 5 5 2 GP DMA Read with Cache Hit 14 17 14 5 6 GP Bus Echo Mode 14 17 14 5 7 Clocking Considerations...

Page 13: ...3 16 5 1 PIT Channel 0 16 3 16 5 2 PIT Channel 1 16 3 16 5 3 PIT Channel 2 16 4 16 5 4 Operating Modes 16 4 16 5 4 1 Mode 0 Interrupt on Terminal Count 16 4 16 5 4 2 Mode 1 Hardware Retriggerable One...

Page 14: ...19 4 19 4 2 Interrupts 19 5 19 4 3 AMDebug Technology Interface 19 5 19 4 4 Software Considerations 19 5 19 5 Initialization 19 6 CHAPTER 20 REAL TIME CLOCK 20 1 20 1 Overview 20 1 20 2 Block Diagram...

Page 15: ...perating Modes 21 9 21 5 5 DMA Interface 21 10 21 5 5 1 Transmit DMA 21 10 21 5 5 2 Receive DMA 21 10 21 5 6 Clocking Considerations 21 10 21 5 7 Interrupts 21 10 21 5 7 1 Serial Port Interrupts 21 12...

Page 16: ...t Mode 24 7 24 4 2 1 Using the Write Buffer Test Mode Interface 24 7 24 4 2 2 SDRAM Write Cycle in Write Buffer Test Mode 24 8 24 4 2 3 SDRAM Read Cycle in Write Buffer Test Mode 24 8 24 4 3 Other Deb...

Page 17: ...26 2 Block Diagram 26 2 26 3 System Design 26 2 26 3 1 Connecting the AMDebug Port 26 2 26 3 2 Mechanical Specifications for the Target Connector 26 4 26 3 3 Locating the Connector on the Target Syst...

Page 18: ...Master Arbitration Queues 8 9 Figure 8 5 Host Bridge Master Arbitration Queue 8 9 Figure 8 6 CPU Bus Arbitration 8 11 Figure 8 7 CPU Bus Cache Write Back 8 13 Figure 8 8 CPU to PCI Cycle 8 14 Figure...

Page 19: ...gure 12 9 Page Access for Fetching Two Doublewords from a 16 Bit ROM 12 11 Figure 12 10 Cache Line Fill Fetching Four Doublewords from a 32 Bit ROM 12 11 Figure 12 11 Word Write Cycle to Flash Memory...

Page 20: ...ull duplex Microwire Compatible Configuration 22 7 Figure 22 9 SSI Timing TC_INT and BSY_STA Bits 22 8 Figure 23 1 PIO Signal Block Diagram 23 2 Figure 24 1 System Test Mode Timing During a SDRAM Writ...

Page 21: ...pped 5 6 Table 6 1 Reset Generation Registers Memory Mapped 6 3 Table 6 2 Reset Generation Registers Direct Mapped 6 3 Table 6 3 lanSC520 Microcontroller Reset Sources 6 4 Table 6 4 States of Cores af...

Page 22: ...k Source 16 6 Table 16 5 PIT External Clock Source 16 6 Table 17 1 General Purpose Timer Signals Shared with Other Interfaces 17 1 Table 17 2 General Purpose Timer Registers Memory Mapped 17 2 Table 1...

Page 23: ...tions diagrams Chapter 2 describes the signals and pins of the lanSC520 microcontroller Logic diagrams showing defaults and pins with shared signals are also found in this chapter Detailed pin state i...

Page 24: ...520 microcontroller Chapter 25 describes the Joint Test Action Group JTAG IEEE Std 1149 1 1990 boundary scan test interface features of the lanSC520 microcontroller Chapter 26 provides an overview of...

Page 25: ...Interest Group 800 433 5177 US 503 693 6360 International www pcisig com IEEE Std 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture order SH16626 NYF Institute of Electrical and El...

Page 26: ...s reserved for compatibility purposes For example the bit field might be ignored during writes to maintain software compatibility If you see a be sure to read the bit description and programming notes...

Page 27: ...about clock generation General field Bit field in a register one or more consecutive and related bits can It is possible to perform an action if properly configured will A certain action is going to o...

Page 28: ...Introduction xxviii lan SC520 Microcontroller User s Manual...

Page 29: ...Distinctive Characteristics Industry standard Am5x86 CPU with floating point unit FPU and 16 Kbyte write back cache 100 MHz and 133 MHz operating frequencies Low voltage operation core VCC 2 5 V 5 V...

Page 30: ...ffers full duplex or half duplex operation Flexible address decoding for programmable memory and I O mapping and system addressing configuration 32 programmable input output PIO pins Native support fo...

Page 31: ...Bus Interface Am5x86 CPU Bus Interface Unit CPU Bus Interface PCI Target PCI Master PCI Bus Arbiter CPU Bus Arbiter Clock Generation FIFOs and FIFO Control GP DMA Address Data Control Status CPU Data...

Page 32: ...velopment tools Integrated floating point unit FPU compliant with ANSI IEEE 754 standard 16 KByte unified cache configurable for either write back or write through cache mode The Am5x86 CPU is describ...

Page 33: ...esultant increase in the memory content reliability enables the lanSC520 microcontroller to be effectively utilized in applications that require more reliable operation such as communications environm...

Page 34: ...pherals on page 1 7 These internal peripherals are designed to operate at the full clock rate of the GP bus The internal peripherals can also be configured to operate in PC AT compatible configuration...

Page 35: ...to the resolution of four clock periods where the clock period is the 33 MHz clock Timer input and output pins provide the ability to interface with off chip hardware A standard PC AT compatible progr...

Page 36: ...twork between the wide area network WAN the internet and a local area network LAN an intranet of computers and information appliances in the home The SRG provides firewall protection of the LAN from u...

Page 37: ...client device that uses a television set as the display Common applications for the DSTB are internet access e mail and streaming audio and video content The minimal system includes a connection to t...

Page 38: ...t Residential Gateway Reference Design lan SC520 Microcontroller GP Bus GPA25 GPA0 GPD15 GPD0 Control MA12 MA0 MD31 MD0 Control SDRAM AD31 AD0 Control PCnet Home WAN Interface Am79C978 32 kHz Crystal...

Page 39: ...erence Design AD31 AD0 Control lan SC520 Microcontroller GP Bus Control Controller VGA LCD Flash PCI Bus SDRAM Bus Am79C973 Am79C975 PCnet Fast III Super I O PS 2 Keyboard PS 2 Mouse Parallel Serial C...

Page 40: ...e Design Flash lan SC520 Microcontroller GP Bus PCI Bus SDRAM Bus EIDE DVD or HDD Control GPA1 GPA0 GPD15 GPD0 MA12 MA0 MD31 MD0 Control SDRAM AD31 AD0 Control NTSC PAL VGA Super I O PS 2 Keyboard PS...

Page 41: ...troller GP Bus SDRAM Bus HDLC PCM Highway T1 or E1 6x to 10X 32 kHz Crystal 33 MHz Crystal MA12 MA0 MD31 MD0 Control SDRAM Control Flash Control Memory ISLIC Am79R241 Quad ISLAC Am79Q2241 ISLIC Am79R2...

Page 42: ...Architectural Overview 1 14 lan SC520 Microcontroller User s Manual...

Page 43: ...e 2 6 PCI bus page 2 6 General purpose GP bus page 2 7 Serial ports page 2 9 Timers page 2 10 Clocks and reset page 2 10 Chip selects page 2 11 Programmable I O PIO page 2 11 JTAG boundary scan test i...

Page 44: ...2 DTR1 DCD2 DCD1 RIN2 RIN1 SSI_CLK SSI_DO SSI_DI 3 XV GPA25 GPA0 GPD15 GPD0 GPRESET GPIORD GPIOWR GPMEMRD GPMEMWR GPALE GPBHE GPRDY GPAEN GPTC GPDRQ3 GPDRQ0 GPDACK3 GPDACK0 GPIRQ10 GPIRQ0 GPDBUFOE GPI...

Page 45: ...D1 RIN1 SSI_CLK SSI_DO SSI_DI 3 XV 520 ODVK GPA25 DEBUG_ENTER GPD15 GPD0 GPRESET GPIORD GPIOWR GPMEMRD GPMEMWR PIO0 GPALE PIO1 GPBHE PIO2 GPRDY PIO3 GPAEN PIO4 GPTC PIO5 PIO8 GPDRQ3 GPDRQ0 PIO9 PIO12...

Page 46: ...efault operation hold state and voltage is available in the lan SC520 Microcontroller Data Sheet order 22003 Connection and package diagrams as well as pin number assignments are also included in that...

Page 47: ...ed on two different pins to reduce the total load connected to CAS Suggested system connection SCASA for SDRAM banks 0 and 1 SCASB for SDRAM banks 2 and 3 SCS3 SCS0 O SDRAM Chip Selects are the SDRAM...

Page 48: ...ring SDRAM read cycles and outputs data during SDRAM write cycles Configuration registers are used to select whether ROMCS2 and ROMCS1 use the GP bus data bus or the MD data bus A reset configuration...

Page 49: ...ite or that the master is ready to accept data read PAR B PCI Parity is driven by the initiator or target to indicate parity on the AD31 AD0 and CBE3 CBE0 buses PERR B Parity Error is asserted to indi...

Page 50: ...24 O GP Bus Data Bus Buffer Output Enable is used to control the output enable on an external transceiver that may be on the GP data bus Using this transceiver is optional in the system design and is...

Page 51: ...for faster rise time GPRESET O GP Bus Reset when asserted re initializes to reset state all devices connected to the GP bus GPTC PIO4 O GP Bus Terminal Count is driven from the internal DMA controller...

Page 52: ...tor is used 32KXTAL1 should be unconnected and the clock source driven on 32KXTAL2 33MXTAL2 33MXTAL1 osc 33 MHz Crystal Interface is the main system clock for the chip This clock source is used to der...

Page 53: ...ble Input Output signals can be programmed as inputs or outputs When they are outputs they can be driven High or Low by programming bits in registers PIO1 GPBHE B PIO2 GPRDY B PIO3 GPAEN B PIO4 GPTC B...

Page 54: ...ing operating system application communication TRIG TRACE O Trigger Trace triggers event to logic analyzer optional from Am5x86 CPU debug registers The AMDebug technology serial parallel interface can...

Page 55: ...resistors CFG0 Choose 8 16 or 32 bit ROM Flash interface for BOOTCS CFG1 DATASTRB WBMSTR1 I CFG1 Choose 8 16 or 32 bit ROM Flash interface for BOOTCS CFG2 CF_DRAM WBMSTR2 I CFG2 When Low when PWRGOOD...

Page 56: ...below 2 0 V the Valid RAM and Time VRT bit in RTC index 0Dh is cleared until read After the read the VRT bit is set until BBATSEN is sensed via a subsequent PWRGOOD assertion BBATSEN also provides a...

Page 57: ...ile media which is generally a disk drive but could be Flash memory or other media The operating system or application begins operating in real mode and then may make its own transition into protected...

Page 58: ...pplication In the above example the switch to simple protected mode line 3 sets the processor CS register and the CS descriptor cache This disables the redirection of the reset region to the reset seg...

Page 59: ...gure the Programmable Address Region PAR registers 15 Configure the interrupt mappings 16 Configure the programmable I O PIO pins 17 Configure the PCI bus controller and arbitration 18 Now the BIOS ca...

Page 60: ...ic software could then examine and report the causes of the last few resets This can be very helpful when trying to determine the cause of system problems Note that the system could record other infor...

Page 61: ...000 0000FFF0 The redirection works because in real mode linear addresses for code fetches are generated by taking the offset in EIP and adding it to the contents of the base register in the CS descrip...

Page 62: ...only RTOS will merely setup the protected mode data structures switch to protected mode and jump directly into system boot code the boot ROM device is the device selected by BOOTCS In contrast a syste...

Page 63: ...owing the change then a subsequent CPUID instruction will report the altered condition of the processor i e the state at the time the soft reset occurred After a hard CPU reset the lanSC520 microcontr...

Page 64: ...ons in an lanSC520 microcontroller system PAR registers are programmed by atomically writing 32 bit values See Programmable Address Region PAR Registers on page 4 5 for more information on using the P...

Page 65: ...lue 03h 0000011b would be programmed into bits 24 18 of a PAR register i e one less than the required number of pages To specify a page count of one all the bits in the SZ_ST_ADR field for a PAR regis...

Page 66: ...e enabled region 1 Write protected region 0 Cacheable region 1 Noncacheable region 0 Code execution permitted 1 Code execution denied 25 Memory Page Size 0 4 Kbyte memory page size on 4 Kbyte boundary...

Page 67: ...3 D J H 6 L H 2 RFDWLRQ DVH 5HJLRQ 6L H 2 WHV 6WDUW GGUHVV RQ E WH RXQGDU 5HJLRQ 6L H E WH 3DJHV 6WDUW GGUHVV RQ WH RXQGDU 5HJLRQ VL H E WH 3DJHV LQDU H LWV LHOGV 7DUJHW HYLFH WWULEXWH 3 D J H 6 L H...

Page 68: ...erify cycle For more information see page 12 12 3 7 2 3 Code Execution Attribute Execution control works in a similar manner to the Write Protect Attribute bit The difference is that when this bit is...

Page 69: ...d to cause memory or I O cycles to be forwarded to the external GP bus This is true for devices that use chip selects and devices that decode their own address generate their own chip selects Programm...

Page 70: ...decoding for each individual A D converter The converters will be memory mapped to a range of 00020000 0002003Fh The PAL generates the chip selects for each of the four converters by watching for the...

Page 71: ...from the PCI to the GP bus using PAR registers TheIO_HOLE_DESTbit intheAddressDecodeControl ADDDECCTL register MMCR offset 80h can be programmed to allow all I O space addresses below the 1 Kbyte boun...

Page 72: ...hat the network adapter has 16 Kbytes of address space that needs to be placed at 000B0000h This area is noncacheable because it is PCI address space As shown in Table 3 7 the value to configure PAR 0...

Page 73: ...Two Banks of Flash for an Execute In Place XIP Operating System A system has eight 8 Mbit byte wide Flash devices Four are on ROMCS1 and four on ROMCS2 These devices will be mapped into eight Mbytes...

Page 74: ...For buffer regions used by GP DMA channels or PCI bus masters disabling caching with a PAR register is more efficient and provides better bus performance than allowing the CPU to cache the buffer This...

Page 75: ...tware that configures interrupts 3 8 1 Edge Sensitive or Level Triggered Interrupts Edge and level triggering can be programmed for each PIC or on an interrupt by interrupt basis For example all of th...

Page 76: ...ers 3 10 CONFIGURING THE PCI HOST BRIDGE AND ARBITRATION The PCI Host Bridge must be configured and initialized before PCI operation such as enumeration and device configuration take place There are t...

Page 77: ...TC and other devices The internal RTC can be disabled by setting the RTC_DIS bit in the Address Decode Control ADDDECCTL register MMCR offset 80h UART 1 and UART 2 can be disabled by setting the UART1...

Page 78: ...System Initialization 3 22 lan SC520 Microcontroller User s Manual...

Page 79: ...the lower 1 Gbyte region via an I O mapped register called the Configuration Base Address CBAR register Port FFFCh The default MMCR region in high memory below the boot space is visible even if it is...

Page 80: ...urce decoding Programmable Address Region 1 PAR1 8Ch General purpose resource decoding Programmable Address Region 2 PAR2 90h General purpose resource decoding Programmable Address Region 3 PAR3 94h G...

Page 81: ...her defines a separate space for configuration registers The lanSC520 microcontroller divides these address spaces as follows Memory space ROM Flash space for data and code storage using up to three c...

Page 82: ...isters that control these interfaces Finally for chip selects see Chapter 23 Table 4 4 Memory and I O Space Summary Device Memory Space I O Space SDRAM Linearspace starting at 00000000h to top of SDRA...

Page 83: ...ce the lanSC520 microcontroller supports PC AT compatible peripherals the regions required for these peripherals are fixed in I O space and are not relocatable via PAR registers This includes the GP b...

Page 84: ...e enabled region 1 Write protected region 0 Cacheable region 1 Noncacheable region 0 Code execution permitted 1 Code execution denied 25 Memory Page Size 0 4 Kbyte memory page size on 4 Kbyte boundary...

Page 85: ...scanbe redirected to ROM GP bus or PCI bus memory via PAR registers or redirected to MMCR space via the CBAR register ROM or SDRAM regions with noncacheable write protected and or execute privilege at...

Page 86: ...I bus master generates a memory write cycle that is forwarded to the memory controller and a PAR has been programmed to write protect the region an SDRAM write cycle will occur with the SDQM signals i...

Page 87: ...discarded 4 3 3 4 PCI Bus Memory Space The lanSC520 microcontroller s address decoding logic automatically defaults all memory space above configured SDRAM to the PCI bus with the exception of the 4 K...

Page 88: ...ng ROM controller PCI host bridge System arbitration Memory and I O space control GP bus controller PIO pin multiplexing and clock control Software timer General purpose timers 0 1 and 2 Watchdog time...

Page 89: ...n the lower 1 Gbyte space on a 4 Kbyte boundary 4 3 4 2 PCI Configuration Space PCI Local Bus Specification Revision 2 2 defines an indirect mapped configuration space that occupies only eight bytes i...

Page 90: ...Configuration Address PCICFGADR register is cleared to 0 Otherwise they are forwarded as a PCI configuration cycle Ports 0CF8 0CFBh are forwarded to the PCI bus as I O transactions only for non doubl...

Page 91: ...e Slave GP DMA Controller 0000 000Fh Master Interrupt Controller 0020 0021h Slave 2 Interrupt Controller This controller is not defined in standard PC AT architecture but has been included in the lanS...

Page 92: ...e 1 will not be accessed on the GP bus as programmed In this case the byte requested must be directly accessed by the CPU at I O address xxx1h This region is not accessible by PCI bus masters 4 3 5 Co...

Page 93: ...For example an I O device can contain multiple integrated functions that are each addressed at separate noncontiguous I O addresses such as a custom ASIC In this case multiple PAR registers can be us...

Page 94: ...gion above the DOS 640 Kbyte application space at 000A0000h area ending at 000FFFFFh 1 Mbyte This space defaults to SDRAM once the SDRAM banks are enabled but the PAR registers can be programmed to su...

Page 95: ...lanSC520 microcontroller can be programmed to generate an interrupt request when a write protection violation occurs providing software with a debugging mechanism to determine which task illegally att...

Page 96: ...that was overlaid since address translation is not supported in the lanSC520 microcontroller For example if a PCI bus video card is used in the 000A0000 000AFFFFh region as in typical PC AT operation...

Page 97: ...ected to the PCI bus byte 1 will not be accessed on the GP bus as programmed In this case the byte requested must be directly accessed by the CPU at I O address xxx1h A write protection violation occu...

Page 98: ...ress spaces enabled Note that I O holes below 1 Kbyte will be directed to the external GP bus However no chip selects are enabled and positive decodes would be required Integrated PC AT peripheral I O...

Page 99: ...may be required in some systems The clocking generation and control features include RTC low current oscillator using standard off the shelf 32 768 kHz crystal 33 MHz oscillator using standard off th...

Page 100: ...Table 5 1 Clock Start up and Lock Times Clock Source Max 32 768 kHz Oscillator 1 s 33 MHz Oscillator 10 ms PLL1 1 47456 MHz 10 ms PLL2 36 864 MHz 100 s PLL3 66 MHz 50 s 32 768 kHz Crystal 32 768 kHz...

Page 101: ...igure 5 2 System Clock Distribution Block Diagram Table 5 2 Clock Signals Shared with Other Interfaces Default Function Alternate Function Control CLKTIMER CLKTEST CLK_PIN_DIR bit in Clock Select CLKS...

Page 102: ...s how far off the actual crystal frequency is from the nominal frequency For a typical 32 768 kHz crystal watch crystal the frequency tolerance is 20 parts per million ppm Frequency tolerance is speci...

Page 103: ...ith the lanSC520 microcontroller The 33 000 MHz frequency provides a better guard band than the 33 333 MHz crystal In practice most PCI devices can tolerate both frequencies but it is important to be...

Page 104: ...or software timer Clock Select CLKSEL C26h CLKTIMER CLKTEST pin enable clock output select options 18 432 MHz or 1 8432 MHz UART PLL1 PLL2 PIT and RTC CLKTIMER or CLKTEST select GP Timer 0 Mode Contro...

Page 105: ...her a 33 000 MHz or 33 333 MHz crystal as the 33 MHz clock source 5 5 1 2 PCI Bus The PCI bus system clock on the lanSC520 microcontroller runs at 33 MHz The PCI bus system clock CLK is described in P...

Page 106: ...e 17 5 5 5 1 9 Software Timer The software timer uses the 33 MHz clock Proper configuration of the software timer requires the programmer to specify in the Software Timer Configuration SWTMRCFG regist...

Page 107: ...should be exercised when programming the CLKTIMER CLKTEST pin as an output since there is no logic to avoid spurious pulses while enabling or changing clock frequencies The target device should be hel...

Page 108: ...Clock Generation and Control 5 10 lan SC520 Microcontroller User s Manual...

Page 109: ...ial cycle type shutdown GP bus reset generation via system reset and software writes PCI bus reset generation via system reset and software writes See Chapter 9 PCI Bus Host Bridge Reset sources can b...

Page 110: ...et waveform diagram is shown in Figure 6 3 on page 6 9 All system resets aside from PWRGOOD pin are on the order of 10 ms while soft resets take 16 CPU clocks See the lan SC520 Microcontroller Data Sh...

Page 111: ...ontrol HBCTL 60h PCI reset RST Watchdog Timer Control WDTMRCTL CB0h Watchdog timer enable WDT reset enable interrupt flag duration of the WDT time out interval System Board Information SYSINFO D70h Sy...

Page 112: ...al PLL start up time is allowed to pass 6 Internal CPU system GP bus and PCI bus resets are deasserted The duration of the system reset is on the order of 10 ms the start up time of the internal PLLs...

Page 113: ...PU bus master PCI host bridge master controller Enabled PCI host bridge target controller Disabled SDRAM controller Disabled No banks are enabled Write buffer and read buffer Disabled ROM controller E...

Page 114: ...is maintained so that the contents of SDRAM are preserved Although the CFG3 CFG0 and RSTLD7 RSTLD0 pins are not latched all other aspects of this type of reset are the same as a system reset The syste...

Page 115: ...64h Triple bus fault A soft reset event is asserted in response to a CPU shutdown cycle due to a triple bus fault Entering AMDebug mode A soft reset event is also asserted in response to a soft reset...

Page 116: ...hese two a20 gate sources are logically ORed such that both sources must be deasserted to cause the CPU s a20 output to be gated Low The SCP a20 gate command is detected when the CPU issues the standa...

Page 117: ...reset event is generated if the RTC voltage monitor has detected a low RTC battery condition 6 Internal PLLs are enabled and clocks become stable internal PLL startup time is allowed to pass 7 Interna...

Page 118: ...Reset Generation 6 10 lan SC520 Microcontroller User s Manual...

Page 119: ...Memory Mapped Register Mnemonic MMCR Offset Address Function lanSC520 Microcontroller Revision ID REVID 00h Product identification major and minor stepping level Am5x86 CPU Control CPUCTL 02h CPU cach...

Page 120: ...Linear Address Bus 32 Bit Data Bus 32 Bit Data Bus 32 24 32 20 2 32 32 32 128 Micro instruction Decoded Instruction Path Code Stream Physical Address pcd pwt 32 Base Index Bus Displacement Bus Bus a3...

Page 121: ...ith the standard Am486 CPU architecture The following differences may be relevant to the user There is no provision for an L2 cache The signals that would be needed are not brought out of the lanSC520...

Page 122: ...roller is always 33 MHz However the Am5x86 CPU core frequency is programmable to be 100 MHz or 133 MHz The clock speed of the Am5x86 CPU core defaults to 100 MHz but can be changed dynamically via the...

Page 123: ...tabilize Interrupts generated to the Am5x86 CPU will be honored only after the Am5x86 CPU is operating again 7 5 INITIALIZATION The Am5x86 CPU included on the lanSC520 microcontroller supports two dif...

Page 124: ...egister and the Am5x86 CPU s write buffers retain the values they had prior to the soft reset A soft reset event clears the NMI_ENB bit in the Interrupt Control PICICR register disabling NMIs This all...

Page 125: ...with CPU access of memory and GP bus Nonconcurrent arbitration mode forces all masters to automatically acquire ownership of both PCI and CPU buses regardless of destination of the cycles PCI bus arb...

Page 126: ...CTL 70h PCI bus parking select concurrent arbitration mode enable PCI bus grant time out interrupt enable PCI Bus Arbiter Status PCIARBSTA 71h PCI bus arbiter grant time out identification and status...

Page 127: ...Control SYSARBCTL register MMCR offset 70h System arbitration defaults to nonconcurrent arbitration mode after reset 8 4 1 1 Nonconcurrent Arbitration Mode Nonconcurrent arbitration mode forces all m...

Page 128: ...he completion of a read as a master Therefore the lanSC520 microcontroller s host bridge must force the CPU off the bus and allow the external master write to complete 3 After asserting boff to the CP...

Page 129: ...serviced see Figure 8 2 Figure 8 2 Skipped Master Example In the example shown in Figure 8 2 assume that M0 has just finished a transaction In this case the next master in the rotating priority queue...

Page 130: ...ncurrency issues due to Am5x86 CPU memory writes Other master write cycles are still snooped however to keep the Am5x86 CPU s cache coherent with external memory In this case the external memory is up...

Page 131: ...e arbitration approach is access based which means a PCI master is only granted the bus when it needs requests the bus except in the case of bus parking discussed in Bus Parking on page 8 10 A simple...

Page 132: ...used to specify the position of each PCI master in the high priority queue Both queues have rotating priority and one low priority master is granted the bus for every rotation of the high priority que...

Page 133: ...Pn Low priority masters LPx Current low priority master selected Priority HP0 HP1 LP0 HP0 HP1 LP1 HP0 HP1 LP2 HP0 HP1 LP3 HP0 HP1 LPn CPU Ext PCI PCI Ext PCI Ext Notes The PCI bus arbiter is configura...

Page 134: ...bus or configured to always park on the Am5x86 CPU If no other PCI masters are requesting the bus the GNT to the current PCI master remains asserted until the current PCI master transaction completes...

Page 135: ...tion Notes In Figure 8 6 the CPU bus master signals are labeled mst_xxx and the Am5x86 CPU signals are labeled cpu_xxx Snooping is not shown in this figure The clk signal denotes the 33 MHz clock sour...

Page 136: ...r samples cpu_hlda asserted from the Am5x86 CPU and grants the bus to the CPU bus master thenext master in the queue by asserting mst_gnt to the CPU bus master Clock 10 The CPU bus master samples mst_...

Page 137: ...ns the bus CPU bus master mst_gnt is asserted Am5x86 CPU cpu_hold cpu_hlda are asserted Clock 2 The CPU bus master initiates an inquire cycle by assertingeads to the Am5x86 CPU Clock 4 The Am5x86 CPU...

Page 138: ...g disabled Figure 8 8 CPU to PCI Cycle Notes The clk signal denotes the 33 MHz clock source and represents both the CPU clock and the PCI clock This diagram does not represent the full synchronization...

Page 139: ...The host bridge samples gnt asserted and begins the PCI transaction Clock 17 The PCI transaction is complete and the host bridge returns cpu_rdy to the Am5x86 CPU ending the Am5x86 CPU to PCI cycle Cl...

Page 140: ...ority master in the rotating priority queue Clock 9 No other masters are requesting the bus so the PCI bus arbiter keeps asserting the GNT1 for master 1 This allows master 1 to continue the transactio...

Page 141: ...k on the last master that acquired the bus it would keep GNT0 asserted and park on master 0 Clock 8 The Am5x86 CPU samples the bus idle and its gnt asserted Note the Am5x86 CPU does not have to start...

Page 142: ...rted and asserts the host bridge request to the CPU bus arbiter The external PCI master GNT0 cannot be asserted until the host bridge is granted the CPU bus If the system arbiter were operating in con...

Page 143: ..._TO_INT_ENB bit is set the PCI Host Bridge Interrupt Mapping PCIHOSTMAP register MMCR offset D14h must be configured to route the interrupt to the appropriate interrupt request level and priority The...

Page 144: ...C520 microcontroller PCI bus arbiter can be controlled in the Arbiter Priority Control ARBPRICTL register MMCR offset 74h through the use of the high priority queue and the relative Am5x86 CPU priorit...

Page 145: ...er latency timers of all masters in the high priority queue is multiplied by the number of masters in the low priority queue because the high priority masters are granted the bus after each low priori...

Page 146: ...at is parked on the bus is able to begin a transaction immediately without having to assert REQ because its GNT is already asserted All other masters have to arbitrate for the bus by asserting REQ and...

Page 147: ...72h By default all external PCI bus master requests are disabled 5 Enable Clear the PCI bus GNT time out interrupt with the GNT_TO_INT_ENB bit in the System Arbiter Control SYSARBCTL register if desir...

Page 148: ...System Arbitration 8 24 lan SC520 Microcontroller User s Manual...

Page 149: ...r long bursts without disconnect when the lanSC520 microcontroller is a target 64 doublewords for both reads and writes Capable of zero wait state burst transfers as a target Support for advanced PCI...

Page 150: ...pin and may require external buffering due to system loading see PCI Clocking on page 9 5 RST the PCI bus reset signal is driven from the lanSC520 microcontroller The optional PCI bus target device i...

Page 151: ...specification for information on physical loading and routing The following PCI signals require pullups FRAME IRDY TRDY STOP DEVSEL PERR and SERR These pullups must be provided externally to the lanS...

Page 152: ...r Device AD31 AD0 CBE3 CBE0 PAR FRAME IRDY TRDY STOP DEVSEL PERR SERR RST INT1 REQx GNTx AD31 AD0 CBE3 CBE0 PAR FRAME IRDY TRDY STOP DEVSEL PERR SERR RST INTA INTD eODQ 6 0LFURFRQWUROOHU PCI Bus Host...

Page 153: ...ces Otherwise external buffering and loading of the CLKPCIOUT pin could delay the clock so that the skew between the PCI host bridge and external PCI bus devices would not meet the PCI bus specificati...

Page 154: ...0 microcontroller simply buffers the 33 MHz crystal input and provides it to the CLKPCIOUT pin Because crystals have inaccuracies it is possible that these inaccuracies cause the period of CLKPCIOUT t...

Page 155: ...posting enable Host Bridge Target Interrupt Control HBTGTIRQCTL 62h Target interrupt or NMI select and interrupt enables delayed transaction time out address parity and data parity Host Bridge Target...

Page 156: ...U Cacheable PCI bus memory SBDONE SBO is not supported The optional CLKRUN pin is not supported Table 9 2 PCI Host Bridge Registers Direct Mapped Register Mnemonic I O Address Function PCI Configurati...

Page 157: ...ate configuration cycles on the PCI bus The Configuration Mechanism 1 as defined in the PCI Local Bus Specification Revision 2 1 is used The PCI Configuration Address PCICFGADR register resides at I O...

Page 158: ...egister Port 0CFCh to access the desired configuration register Figure 9 7 PCI Configuration Address PCICFGADR Register For example to access the Status Command PCISTACMD register PCI index 04h double...

Page 159: ...x86 CPU can also generate memory and I O read and write transactions on the PCI bus As a PCI bus master the lanSC520 microcontroller does not generate the following cycles Dual address cycles for 64 b...

Page 160: ...is feature When the time out counter expires a cycle was retried unsuccessfully n times on the PCI bus the cycle is discarded and an interrupt can be generated For a read cycle the data returned is al...

Page 161: ...this example there is no arbitration delay the arbiter is parked on the host bridge If another external PCI bus master was granted the bus or the bus was not idle FRAME assertion would be delayed unt...

Page 162: ...wn in Figure 9 9 This example is the same as a regular read see Section 9 5 3 4 1 until Clock 9 Clock 9 The target asserts STOP with TRDY deasserted signaling a retry The target may add up to 16 waits...

Page 163: ...he PCI bus I O and configuration writes are not posted Figure 9 10 CPU Posted Write Cycle to the PCI Bus Notes The clk signal denotes the 33 MHz clock source and represents both the CPU clock and the...

Page 164: ...n 2 2 compliant target can add up to 16 wait states that would delay the transaction completion A PCI bus target can also retry the PCI transaction In this case the host bridge continues to generate t...

Page 165: ...up to 16 wait states that would delay the transaction completion A PCI bus target can also retry the transaction In this case the host bridge continues to generate the same transaction until the targ...

Page 166: ...ters This space is defined as a linear region starting at the lowest address 00000000h and ending at the top of SDRAM depending on the amount populated in the system a maximum of 256 Mbytes The SDRAM...

Page 167: ...read into the target read FIFO Only the first doubleword requested needs to be read into the target read FIFO before the PCI host bridge completes the delayed transaction instead of retrying it again...

Page 168: ...ites has completed internally In all cases only a maximum of one delayed read transaction can be latched into the address FIFO If two read transactions are received the target controller only latches...

Page 169: ...PCI host bridge would generate single non burst write cycles to address 10008h and 1000Ch After these two write cycles the transaction would be cache line aligned so the PCI host bridge would complet...

Page 170: ...rd or any number greater than 32 and less than 64 in this case this write will cause a purge 9 5 4 9 PCI Host Bridge Target Bus Cycles This section describes in detail the cycles generated by an exter...

Page 171: ...dicates it is willing to burst more data by keeping FRAME asserted the host bridge issues a disconnect by deasserting TRDY and asserting STOP see Section 9 5 4 9 3 The external master can insert wait...

Page 172: ...host bridge latches the transaction information and will prefetch the requested read data This is now a delayed transaction and the PCI bus master is required to relinquish bus ownership and re arbit...

Page 173: ...read FIFO becomes empty Clocks 17 19 The external PCI master reads the data from the PCI host bridge Although the figure shows it this way note that SDRAM having the data by Clock 17 is quite optimis...

Page 174: ...ster read cycles so TRDY is deasserted and STOP is asserted signaling a disconnect Because TDRY is deasserted Clock 4 is the last valid data phase Note that FRAME is still asserted signaling that the...

Page 175: ...to which interrupts the Master Interrupt Command Identification M_CMD_IRQ_ID and Master Interrupt Address Identification M_AD_IRQ_ID fields correspond Status bits in the Status Command PCISTACMD regis...

Page 176: ...e write transactions to PCI are always non burst There are a few cases when the CPU bursts up to two doublewords on a read transaction For simplicity in these cases the PCI host bridge breaks up any A...

Page 177: ...relinquishes ownership of the CPU bus 9 6 INITIALIZATION The PCI bus RST signal when asserted resets the lanSC520 microcontroller s PCI host bridge as well as any external PCI bus devices The RST sign...

Page 178: ...except during a PCI bus initialization after a system or programmable reset A PCI bus 2 2 compliant target is not required to meet the normal initial latency time limit if it is accessed during the 2...

Page 179: ...posted writes when the write buffer is enabled 10 2 BLOCK DIAGRAM The SDRAM controller and its interface to the system SDRAM along with the write buffer and the read buffer are shown in Figure 10 1 Th...

Page 180: ...ram Read Buffer Write Buffer SDRAM Address Decode CPU Interface MD31 MD0 BA1 BA0 MECC6 MECC0 SDQM3 SDQM0 CLKMEMOUT CLKMEMIN SCASB SCASA SRASB SRASA SWEB SWEA Clock Generator 66 MHz 33 MHz 32 kHz SCS3...

Page 181: ...nd test logic is not shown MA12 MA0 MECC6 MECC0 SDQM3 SDQM0 CLKMEMOUT CLKMEMIN SCASB SCASA SRASB SRASA SWEB SWEA MD31 MD0 SCS3 SCS0 Page Bnk x5_addr 27 2 MA Gen Control x5_control 66 MHz PLL Write Buf...

Page 182: ...connected to the DQM of the device that stores the 7 bit check word D 31 24 D 23 16 D 15 8 D 7 0 Bank 3 Bank 1 Bank 2 Bank 0 SWEB MA12 MA0 MD31 MD0 MECC6 MECC0 SWEA SDQM3 DQM 0 D 38 32 SCS2 SCS1 SCS0...

Page 183: ...SRASB SCASA SCASB and SWEA SWEB signals are device command signals that are encoded by the SDRAM controller to send a command to the SDRAM devices Each device in the array must sample these signals S...

Page 184: ...e a direct feedback version of CLKMEMOUT The SDRAM controller s data buffers use CLKMEMIN to latch read data coming from the SDRAM devices CLKMEMIN is used to compensate for delays associated with boa...

Page 185: ...resented by the clock driver Figure 10 6 Alternate SDRAM Clock Generation with External Clock Driver The delays that the system designer must take into consideration are identified by this equation TA...

Page 186: ...al but for a 4 bank configuration of 4 bit devices the capacitance of the interface increases The lanSC520 microcontroller provides programmable drive strength buffers on all address data and control...

Page 187: ...us MD31 MD0 is shared with the ROM Flash controller It is advisable to consider loading issues on the MD31 MD0 bus when both SDRAM and ROM Flash devices are installed Heavy loading by SDRAM and ROM Fl...

Page 188: ...C enable interrupt enable for single bit and multi bit error detection ECC Status ECCSTA 21h Single bit and multi bit error status ECC Check Bit Position ECCCKBPOS 22h ECC data bit position in check b...

Page 189: ...Correction Code ECC is also supported for SDRAM devices to ensure data integrity for these high speed devices 10 5 1 SDRAM Support The lanSC520 microcontroller sources a 66 MHz clock CLKMEMOUT to dri...

Page 190: ...by the column address configuration provided for each bank On page misses a row address followed by a column address is generated during an SDRAM access On page hits only a column address is generate...

Page 191: ...e the column width exceeds the row width dimension Table 10 8 SDRAM Devices Supported with Column Boundary Specification Column Width Density Banks Organization Device Architecture Device Count per Ba...

Page 192: ...2M x 32 x 4 banks 1 12 9 14 bit 32 Mbytes 10 bit 16 Mbit 2 4M x 4 2M x 4 x 2 banks 8 11 10 12 bit 16 Mbytes 64 Mbit 2 16M x 4 8M x 4 x 2 banks 8 13 10 14 bit 64 Mbytes 8M x 8 4M x 8 x 2 banks 4 12 10...

Page 193: ...16M x 4 4M x 4 x 4 banks 8 11 11 13 bit 64 Mbytes 128 Mbit 2 32M x 4 16M x 4 x 2 banks 8 13 11 14 bit 128 Mbytes 16M x 8 8M x 8 x 2 banks 4 12 11 13 bit 64 Mbytes 8M x 16 4M x 16 x 2 banks 2 11 11 12...

Page 194: ...ECC circuit to determine if errors have occurred in storing or retrieving data If there is a single bit error in the 32 bit data word or check bits the ECC circuit flags an error latches the error gen...

Page 195: ...te buffer provides write merge and write collapse functions to better utilize FIFO storage and reduce the number of transactions to SDRAM The read merge function is also provided to reduce data cohere...

Page 196: ...Request Speed RFSH_SPD bit field in the SDRAM Control DRCCTL register MMCR offset 10h and offers either 7 8 s 15 6 s 31 2 s or 62 5 s periods Note Since the minimum refresh rate is 62 5 s which is bel...

Page 197: ...ection The lanSC520 microcontroller provides selectable drive strength options on all address data and control signals to provide support for different SDRAM device loads presented by different system...

Page 198: ...ation changes This places the SDRAM devices in an idle state and clears the SDRAM controller s page table entries See SDRAM Device Initialization on page 10 30 for more information 10 5 6 SDRAM Timing...

Page 199: ...parameter is specified in the RAS_CAS_DLY bit field of the SDRAM Timing Control DRCTMCTL register MMCR offset 12h 10 5 6 4 RAS to RAS or Auto Refresh to RAS TRC The RAS to RAS or auto refresh to RAS p...

Page 200: ...od for a 33 333 MHz crystal A minimum TRAS of 5T is enforced when a TRCD of 2T is specified 10 5 7 Bus Cycles 10 5 7 1 SDRAM Burst Read Cycle The lanSC520 microcontroller always bursts up to four doub...

Page 201: ...rget GP DMA All the writes are configured for single write mode with each write occurring independently Am5x86 CPU non burst write transfers are shown in Figure 10 8 An Am5x86 CPU burst write cycle is...

Page 202: ...of overhead occurs during a full doubleword write to the SDRAM In the case of a read however the ECC has to generate the new check bits check for any errors and generate an interrupt if an error occu...

Page 203: ...of a read modify write cycle as shown in Figure 10 11 As shown a write cycle with a partial doubleword requires an SDRAM read cycle followed by a write cycle Note that the SDRAM read burst is termina...

Page 204: ...ed each time a refresh is required The internal banks will be precharged and idle for a minimum of the Precharge time TRP before the Auto Refresh command is applied When the refresh cycle has complete...

Page 205: ...rrors Separate interrupts can be generated for both single bit error and multi bit error detection These two interrupts are routed from the SDRAM controller to the lanSC520 microcontroller s programma...

Page 206: ...onfiguration it is important to not enable an SDRAM bank with the Bank Ending Address specified as 0 10 5 9 3 Write Protection Regions of SDRAM can be write protected through the use of a Programmable...

Page 207: ...for errors the respective interrupt is generated if an error is detected 2 The new ECC code is generated to include the data just read and the new data to be written 3 The complete modified doubleword...

Page 208: ...DRAM is enabled the ECC operation requires that SDRAM and its associated ECC memory be initialized This is accomplished by the boot code that must write to every location in SDRAM This process initial...

Page 209: ...ith a binary pattern of 100b being written to the Operation Mode Select bits The boot code must perform at least two accesses to SDRAM when in this mode 10 6 2 5 Mode Register Programming Once the Aut...

Page 210: ...vices before they are functional SDRAM device initialization is discussed in more detail in Section 10 6 2 Note that SDRAM refresh cycles should only be enabled when the OPMODE_SEL bit field is config...

Page 211: ...liasing to determine the actual size of the external SDRAM bank Note that while SDRAM sizing is being performed the Am5x86 CPU cache the SDRAM ECC the SDRAM write buffer and the SDRAM read ahead featu...

Page 212: ...the patterns given in the example the value read is the number of real columns for the external bank 10 6 4 2 Determining the Number of Internal Banks Determining the correct number of internal banks...

Page 213: ...k 9 If the pattern read from address7 is pattern7 or pattern8 then four internal banks exist 10 If the pattern read from address7 is anything other than pattern7 pattern8 or pattern9 then there is no...

Page 214: ...SDRAM Controller 10 36 lan SC520 Microcontroller User s Manual...

Page 215: ...cache line This feature is provided in anticipation of future accesses to the prefetched line spatial locality The read buffer is always enabled however the read ahead feature and write buffer are dis...

Page 216: ...during master write cycles or write buffer write cycles that hit an existing line in the read buffer Data coherency during all configuration changes of the individual features is performed in hardwar...

Page 217: ...fect the other functions of these pins so they Read Merge x5_wr_data 31 0 Write Buffer Address Debug Tag Storage 32 ranks wb_data 31 0 Address Tag Byte Valid Bits Master Trace Bits wb_ad 27 2 Byte 2 B...

Page 218: ...master read accesses that result in a burst of two or more doublewords A prefetch never occurs for a GP DMA request since GP DMA read requests are never burst However during a GP DMA read request the...

Page 219: ...or around write buffer requests Write buffer requests are due to write data that was posted during previous master write activity and is migrating to SDRAM Read around write is only functional when t...

Page 220: ...s are not performed This results in less overhead to maintain data coherency Should a read occur to an address contained in the write buffer the write buffer merges its data with the data returned fro...

Page 221: ...MA Write Byte Adrs 0FBB000 Data 88h 2 DMA Write Byte Adrs 0FBB001 Data 92h 3 DMA Write Byte Adrs 0FBB002 Data 44h 1 DMA Write Byte Adrs 0FBB000 Data 88h 2 DMA Write Byte Adrs 0FBB001 Data 92h 3 DMA Wr...

Page 222: ...from SDRAM will be replaced with the more recent doubleword in the write buffer Read merging maintains data coherency and enhances SDRAM performance by not requiring a flush of the write buffer conte...

Page 223: ...ws the write buffer to fill higher prior to requesting SDRAM service resulting in a greater chance of write data merging or collapsing A lower watermark setting can be used for applications that requi...

Page 224: ...master as it occurs When the read ahead feature is enabled a read ahead prefetch only occurs for master demand burst requests of two or more doublewords The read ahead feature takes advantage of the l...

Page 225: ...ing cache line fills the Am5x86 CPU can maintain bus tenure for more than one burst transfer such that successive bursts will be satisfied by read buffer prefetch hits Also during PCI master read burs...

Page 226: ...to empty quickly This prevents the PCI master from experiencing the SDRAM latencies thus freeing up the PCI bus earlier During PCI target write transfers to SDRAM the Am5x86 CPU cache is snooped to ma...

Page 227: ...that location during sizing or if SDRAM is functional at that location during test Since the write buffer provides a read merging function to reduce the overhead associated with maintaining data cohe...

Page 228: ...RAM This would reduce the total number of SDRAM writes cycles from 64 to 16 in this example The write buffer also improves memory system performance during heavy SDRAM write data thrashing between mul...

Page 229: ...etch configuration are not preserved during a programmable reset See Chapter 6 Reset Generation for more detailed information on this type of reset It is recommended that prior to SDRAM sizing and tes...

Page 230: ...Write Buffer and Read Buffer 11 16 lan SC520 Microcontroller User s Manual...

Page 231: ...grammable timing for both non page mode and page mode devices is supported Programmable Address Region PAR register attributes provide code execution control cacheabilitity control and write protectio...

Page 232: ...DRAM or GP bus data bus on which the ROM is located The CFG1 CFG0 pins define the data width of the ROM devices CFG2 CFG0 are latched when PWRGOOD is asserted See Initialization on page 12 14 for more...

Page 233: ...ssary when using the same bus for 5 V ROM devices and 3 3 V SDRAM devices that are not 5 V tolerant For example if the 3 3 V SDRAM devices are not 5 V tolerant and share the data bus with 5 V ROM devi...

Page 234: ...Am5x86 CPU performs a read from a ROM device that is on the GP bus data bus the buffer on the SDRAM bus which isolates the ROM devices from the SDRAM activates unless its buffer control pins were als...

Page 235: ...chapter discusses different configurations and operating modes that are appropriate for these varying situations 12 5 1 ROM Support Each of the three chip selects included on the lanSC520 microcontro...

Page 236: ...gnals bs8 and bs16 are asserted based on data size of the selected ROM device 12 5 1 1 Supported Device Types The ROM controller supports two ROM device types Non page mode ROM A ROM device that alway...

Page 237: ...o determine the width of the boot device BOOTCS For all other ROM devices ROMCS1 and ROMCS2 this configuration information must be programmed by the initialization software The WIDTH bit field in the...

Page 238: ...ecified in the FIRST_DLY bit field The delay for subsequent accesses for page mode only is specified in the SUB_DLY bit field Table 12 4 shows the access timing according to the programmed wait states...

Page 239: ...see Table 12 5 12 5 3 1 Single CPU Read Access Figure 12 7 shows an example for the fetching of 16 bits of data GPD15 GPD0 from an 8 bit non page mode ROM configured for one wait state The transfer st...

Page 240: ...ycle Figure 12 8 Page Access for Fetching Four Doublewords from a 32 Bit ROM Burst Sequence 2 1 1 1 During burst transfers to ROM devices with a data width smaller than 32 bits the ROM controller exec...

Page 241: ...in Figure 12 10 Figure 12 10 Cache Line Fill Fetching Four Doublewords from a 32 Bit ROM 12 5 3 4 Writing to Flash Devices The lanSC520 microcontroller supports writable Flash devices Since Flash dev...

Page 242: ...region from FFFF0000 FFFFFFFFh is defined at system reset to handle early code fetches from the boot ROM See Chapter 3 System Initialization and Chapter 4 System Address Mapping for further details o...

Page 243: ...can take from 1 s to up to 10 s near the end of the serviceable life of the device Both the program command sequence and the status read have implications for the use of the lanSC520 microcontroller i...

Page 244: ...n Table 12 6 CFG2 defines whether the boot device is located on the SDRAM data bus or GP bus data bus CFG1 CFG0 define the data width of the boot device BOOTCS is forced active at system reset Boot co...

Page 245: ...GP bus controller 13 3 SYSTEM DESIGN Table 13 1 shows GP bus signals shared with other interfaces on the lanSC520 microcontroller The pinstrap functions associated with the GPA25 GPA14 pins are sampl...

Page 246: ...mmable WDT UART1 UART2 PIC RTC Internal GP Bus PIO GPCS7 GPDRQ0 33 MHz m io r w GPDBUFOE Reset GPRESET bs8 bs16 be3 be0 Divider MUX dior diow gior giow gmemr gmemw gaen dmemr dmemw daen Echo mode sele...

Page 247: ...ister MMCR offset C22h PIO26 GPMEMCS16 PIO26_FNC PIO25 GPIOCS16 PIO25_FNC PIO24 GPDBUFOE PIO24_FNC PIO23 GPIRQ0 PIO23_FNC PIO22 GPIRQ1 PIO22_FNC PIO21 GPIRQ2 PIO21_FNC PIO20 GPIRQ3 PIO20_FNC PIO19 GPI...

Page 248: ...the AND gate in Figure 13 2 is not required The GPIORD pin can be used to control the direction of the data transceiver A similar simplification can be applied if all devices are memory mapped using t...

Page 249: ...RD or GPMEMWR GP Chip Select Recovery Time GPCSRT C08h Chip select recovery time of a GP bus cycle GP Chip Select Pulse Width GPCSPW C09h Width of the chip select signal from the offset GP Chip Select...

Page 250: ...O accesses These chip selects are asserted for Am5x86 CPU accesses to the corresponding regions set up in the Programmable Address Region PAR registers Four external DMA channels provide fly by DMA t...

Page 251: ...djustable GP bus timing parameters The actual time can be calculated with the following formula REG_VAL 1 TCLK where REG_VAL register content value TCLK internal clock period The minimum offset pulse...

Page 252: ...bus echo mode are shown in Table 13 3 GPA25 GPA0 GPCS GPMEMRD or GPIORD GPMEMWR or GPIOWR GPALE GPCSOFF 1 GPRDOFF 1 GPWROFF 1 GPCSPW 1 GPRDW 1 GPWRW 1 GPALEW 1 GPCSRT 1 Bus cycle duration Beginning o...

Page 253: ...ly qualify a chip select that chip select is not asserted for memory read accesses In a typical system environment the command strobes are usually shorter than the chip selects and in such cases the e...

Page 254: ...ler at a time no conflict is possible Note that the GP bus DMA controller can initiate an access on the GP bus Since the GP busDMA controller must already owntheAm5x86CPU s bus before it caninitiate a...

Page 255: ...17 but note that because the Am5x86 CPU itself does not support address pipelining address pipelining is not supported on the GP bus GPA25 GPA24 is added to increase the GP bus address space up to 64...

Page 256: ...der 22003 for information on the GP bus and GP DMA timing supported by the lanSC520 microcontroller ISA Signal Name GP Bus Signal Name AEN GPAEN BALE GPALE BCLK Not Supported DACK GPDACK DRQ GPDRQ IOC...

Page 257: ...igure 13 5 lan SC520 Microcontroller Interfacing with a Super I O Controller Table 13 5 Example Super I O Controller Interface Timing1 Notes 1 This example assumes that a 33 333 MHz crystal is being u...

Page 258: ...troller Table 13 6 and Figure 13 8 show the interfacing timing example In this example the programmable interface timing registers can be programmed using the equation from Programmable Bus Interface...

Page 259: ...used in the system GP Bus Signal Type Offset Register Value Offset Time ns Chip Require ment ns Pulse Width Register Value Pulse Width ns Chip Require ment ns Recovery Time Register Value Recovery Tim...

Page 260: ...WR and GPMEMRD are used instead of GPIOWR and GPIORD Figure 13 9 shows the timing diagram of an 8 bit device access of an 8 bit I O device Figure 13 9 8 Bit Data Access of an 8 Bit I O Device Address...

Page 261: ...but the consecutive 8 bit data accesses are resolved by the Am5x86 CPU transparent to software For memory mapped I O accesses GPMEMRD and GPMEMWR are used instead of GPIORD and GPIOWR When the Am5x86...

Page 262: ...e 13 5 9 5 32 Bit Data Access of a 16 Bit I O Device A 32 bit data access of a 16 bit I O device requires two consecutive 16 bit accesses of the device but the consecutive 16 bit data accesses are res...

Page 263: ...16 bit data bus width The GP bus controller also supports dynamic bus sizing through the GPIOCS16 and GPMEMCS16 pins These pins can be used to override the programming of the data width for the curre...

Page 264: ...tion of the cycle The control signals are always asserted for a minimum of the entire period as programmed in the timing control registers Then the additional delay can be inserted by the deassertion...

Page 265: ...be generated and neither the GP DMA or an external PCI bus master can access SDRAM 13 5 11 2 Slow GP Bus Cycles If the interface timing is programmed to have slow GP bus cycles or if GPRDY is used to...

Page 266: ...ripherals When this signal is asserted all devices connected to the GP bus should re initialize to their reset state To enable the GP bus controller 1 Configure the address decoding region for each ch...

Page 267: ...t to PC AT compatible mode three 16 bit and four 8 bit Buffer chaining capability Variable clock modes 4 8 and 16 MHz Transfers to and from SDRAM only No transfers are possible to PCI ROM or peer GP b...

Page 268: ...ACK0 rxdrq 1 0 txdrq 1 0 rxdack 1 0 txdack 1 0 GPA25 GPA0 GPD15 GPD0 GP DMA Controller UARTs dramrd dramwr addr 27 0 Bus breq bgnt dmemw dmemr GP Bus daddr 27 0 lan SC520 Microcontroller Interface Uni...

Page 269: ...pt Note that qualifying GPTC with a specific GPDACKx signal provides a more specific interrupt For an application that requires a DMA transfer every fixed interval of time a timer output TMROUT1 or TM...

Page 270: ...set C20h PIO11 GPDACK1 PIO11_FNC PIO10 GPDACK2 PIO10_FNC PIO9 GPDACK3 PIO9_FNC PIO8 GPDRQ0 PIO8_FNC PIO7 GPDRQ1 PIO7_FNC PIO6 GPDRQ2 PIO6_FNC PIO5 GPDRQ3 PIO5_FNC PIO4 GPTC PIO4_FNC PIO3 GPAEN PIO3_FN...

Page 271: ...MA mode GP DMA Channel 7 Extended Transfer Count GPDMAEXTTC7 D93h Bits 23 16 of Channel 7 transfer count value enhanced GP DMA mode Buffer Chaining Control GPDMABCCTL D98h Buffer chaining enables for...

Page 272: ...t Transfer Count Low GPDMANXTTCL3 DB0h Bits 0 15 of the next transfer count for Channel 3 when using buffer chaining enhanced GP DMA mode GP DMA Channel 3 Next Transfer Count High GPDMANXTTCH3 DB2h Bi...

Page 273: ...f the transfer count for the GP DMA transactions Channel 2 Page Channel 3 Page Channel 1 Page Channel 0 Page Channel 6 Page Channel 7 Page Channel 5 Page GPDMA2PG GPDMA3PG GPDMA1PG GPDMA0PG GPDMA6PG G...

Page 274: ...MA transfers on the lanSC520 microcontroller The GP DMA initiator is the I O device that asserts GPDRQx This is always an external I O device or memory mapped I O device residing on the GP bus or the...

Page 275: ...to any of the default 8 bit channels channels 0 3 For a read transfer the UART asserts its request from the transmit channel txdrq waits for the acknowledge txdack and latches the data from the low b...

Page 276: ...it for a total of four requests GP bus using GPDRQ3 GPDRQ0 and GPDACK3 GPDACK0 8 bit or 16 bit Table 14 5 shows the lanSC520 microcontroller resource and the GP DMA channels to which the resource can...

Page 277: ...only via the TRNMOD field in the Master DMA Channel 4 7 Mode MSTDMAMODE register Port 00D6h 14 5 3 1 1 8 Bit Transfers Channels 0 3 support 8 bit data transfers between 8 bit I O devices and system SD...

Page 278: ...e the GP DMA controller performs one transfer each time it is granted the Am5x86 CPU bus The GP DMA initiator asserts GPDRQx and holds it active as long as it has data to be transferred The initiator...

Page 279: ...ycle to the associated device A write transfer shown in Figure 14 4 consists of an I O read cycle followed by a memory write cycle to the address in the current address register Depending on the GP DM...

Page 280: ...registers are automatically restored to the values in the base address and base count registers of the given channel following the terminal count This feature is useful when data quantities of the sa...

Page 281: ...ata into two SDRAM buffers when receiving packets Buffer chaining mode is enabled by setting the appropriate CHx_BCHN_ENB bit in the Buffer Chaining Control GPDMABCCTL register MMCR offset D98h 1 The...

Page 282: ...o SDRAM Figure 14 6 shows a GP DMA read cycle in demand transfer mode Figure 14 6 GP DMA Read in Demand Transfer Mode Table 14 8 GP DMA Cycle Types GP DMA Initiator GP DMA Target Data Transfer Directi...

Page 283: ...accesses In normal operation GP bus echo mode disabled the GP bus controller never asserts GPAEN However accesses initiated by the GP bus DMA controller are not affected by enabling the GP bus echo m...

Page 284: ...xt Address registers and the Next Transfer Count registers are both split up into two 16 bit registers the Low and High words have been placed so that they can be accessed using 32 bit instructions Al...

Page 285: ...000Dh and the Master DMA Controller Reset MSTDMARST register Port 00DAh respectively The GP DMA controller is enabled after system reset but all channels are masked off This is also the state after th...

Page 286: ...e 8 bit channels Any internal request from the UART serial ports can be mapped to Channel 3 for the enhanced GP DMA mode features The 8 bit external devices can be mapped to channels 3 5 6 and 7 The f...

Page 287: ...ster Port 00D6h and unmask Channel 4 Also set the CH3_ALT_SIZE bit in the GP DMA Control GPDMACTL register MMCR offset D80h 3 Program the operating frequency if not using the default 4 MHz 4 Enable en...

Page 288: ...GP Bus DMA Controller 14 22 lan SC520 Microcontroller User s Manual...

Page 289: ...programmable interrupt router to route the sources to be used as ISA interrupts to the appropriate interrupt channels of the Slave 1 and Master controllers PCI interrupts are level sensitive shareabl...

Page 290: ...ESIGN Table 15 1 shows PIC signals shared with other interfaces When enabled the multiplexed signals shown in Table 15 1 either disable or alter any other function that uses the same pin The GPIRQ10 G...

Page 291: ...1_irq pit_tmr2_irq uart1_irq rtc_irq Timers UARTs RTC WDT SSI ssi_irq SDRAM ecc_irq Control signals Configuration Registers Control Logic Interrupt Router intr nmi wdt_irq uart2_irq irq_p1 irq_p2 s1_i...

Page 292: ...17 NMI Control SWINT22_17 D0Ah Software interrupt generation control priority level 17 22 software NMI generation to the CPU Interrupt Pin Polarity INTPINPOL D10h Polarity of external interrupt sourc...

Page 293: ...t channels or NMI Write Protect Violation Interrupt Mapping WPVMAP D44h Write protect violation to PAR interrupt mapping to any of 22 available interrupt channels or NMI AMDebug Technology RX TX Inter...

Page 294: ...Interrupt request service status Master PIC Initialization Control Word 1 ICW1 Slave 2 PIC Initialization Control Word 1 ICW1 Slave 1 PIC Initialization Control Word 1 ICW1 MPICICW1 S2PICICW1 S1PICICW...

Page 295: ...rupt request If no interrupt request is active when the acknowledgement occurs then the affected master or slave PIC returns the interrupt entry number associated with its IR7 input However in this ci...

Page 296: ...rs from the interrupt sequence mentioned above Steps 3 5 are similar in this case but because the Interrupt Request xIR register bit set by the slave output is the highest priority interrupt the Maste...

Page 297: ...e the SDRAM ECC multi bit error NMI source and the PCI host bridge s separate NMI only source 18 can be routed to the Am5x86 CPU s NMI input The only source that cannot be used to generate an NMI is t...

Page 298: ...rrupt channel This is discussed further in Interrupt Sharing on page 15 13 After reset each of the interrupt sources must be mapped to the desired interrupt channel This is usually done by the initial...

Page 299: ...nb24 src_enb25 src_enb26 irq 1 _trig pci_irq src_enb27 0 1 GPIRQ10 polarity10 src_enb10 1 0 INTA polarity11 src_enb11 1 0 INTD polarity14 src_enb14 ssi_irq wpv_irq src_enb28 src_enb29 gpdma_bc_irq ice...

Page 300: ...15 4 PC AT Interrupt Channel Mapping PC AT Compatible System lanSC520 Microcontroller IRQ I O Device Priority Interrupt Source to Map IRQ0 System Timer 0 P1 Internal PIT 0 interrupt IRQ1 Keyboard int...

Page 301: ...sis A bit is provided for each of the 22 interrupt channels for interrupt type programmability The selection between global and per channel interrupt mode is done via software However the original glo...

Page 302: ...ring NMIs NMIs can be shared in the lanSC520 microcontroller NMI sources are routed logically to an OR gate as shown in Figure 15 4 on page 15 15 Each individual interrupt source is gated by an enable...

Page 303: ...6 nmi_enb17 nmi_enb18 nmi_enb19 nmi_enb20 nmi_enb21 nmi_enb22 nmi_enb23 nmi_enb24 nmi_enb25 nmi_enb26 NMI to CPU 0 1 0 1 0 1 0 1 pci_irq gpdma_bc_irq nmi_enb28 nmi_enb29 nmi_trig pci_nmi nmi_enb27 nmi...

Page 304: ...P22 and is a variation of the specific rotation type In automatic rotation scheme all priority levels within the controller are treated as equal In this mode an interrupt request after being serviced...

Page 305: ...controllers are arranged in the lanSC520 microcontroller For example the Slave 1 PIC Initialization Control Word 3 S1PICICW3 register Port 00A1h always contains 2d to indicate that Slave 1 is hooked u...

Page 306: ...ars the A10 A8 bit field bits 2 0 which should be 0 for PC AT compatible interrupts 5 The SFNM and AEOI bits must be cleared to 0 in the Master PIC Initialization Control Word 4 MPICICW4 register Port...

Page 307: ...ain active long enough for the corresponding In Service xISR register bit to be set a non deterministic amount of time the request is considered a spurious interrupt pulse Spurious pulses on any of th...

Page 308: ...quests are gated off This effectively disables all interrupt requests from reaching the CPU At system reset the PIC is disabled 1 Configure the Master Slave 1 and Slave 2 controllers as described in C...

Page 309: ...for PIT Channel 2 Several modes of operation including Interrupt on terminal count Hardware retriggerable one shot Rate and square wave generation Hardware and software retriggerable strobe 16 2 BLOCK...

Page 310: ...unction Chip Select Pin Function Select CSPFS C24h GPCS3 or PITGATE2 function select Clock Select CLKSEL C26h CLKTIMER CLKTEST pin enable clock output select options PIT CLKTIMER select input clock fo...

Page 311: ...s only modes 0 2 3 and 4 Mode 0 is typically used for interrupts because it remains in the High state until restarted Table 16 3 Programmable Interval Timer Configuration Registers Direct Mapped Regis...

Page 312: ...o the PIT Channel x Count PITxCNT register the output of the counter goes Low 2 The count value decrements by one for each input clock pulse if the gate input is held High 3 If the gate input is held...

Page 313: ...initial count is an odd number the output is High for n 1 2 cycles and is Low for n 1 2 cycles By default PC AT compatible systems program PIT channels 1 and 2 to use this mode to drive DRAM refresh a...

Page 314: ...a Low to High signal on terminal count and they are usually used as interrupt sources 16 5 7 Software Considerations 16 5 7 1 Using the PIT Clock Source in PC AT Compatible Systems In PC AT compatibl...

Page 315: ...lect CLKSEL register MMCR offset C26h is used for this purpose 16 6 INITIALIZATION At system reset the state of the PIT itself is undefined The mode count value and output of all channels are undefine...

Page 316: ...Programmable Interval Timer 16 8 lan SC520 Microcontroller User s Manual...

Page 317: ...1 used for external event capture pulse count and counter reset reload One external output pin for GP Timer 0 and GP Timer 1 One interrupt output for each timer Several modes of operation including I...

Page 318: ...t retrigger internal clock source prescaler external clock source alternate compare mode continuous mode GP Timer 0 Count GPTMR0CNT C74h Current count value GP Timer 0 Maxcount Compare A GPTMR0MAXC MP...

Page 319: ...ny functions via the use of the configuration bits in the respective timer registers These functions include Clock input Configured with the EXT_CLK bit in the GP Timer x Mode Control GPTMRxCTL regist...

Page 320: ...B GPTMRxMAXCMPB register lets the timer alternate between two maximum values This mode is enabled with the ALT_CMP bit in the GP Timer x Mode Control GPTMRxCTL register In alternate compare mode the...

Page 321: ...is programmed to use both of its GP Timer Maxcount Compare registers and the ALT_CMP and CONT_CMP bits are set in the GP Timer x Mode Control GPTMRxCTL register the timer output pin TMROUT0 or TMROUT...

Page 322: ...s A timer s corresponding interrupt status bit is set when that timer s interrupt request signal is asserted and remains set until cleared 17 5 7 Software Considerations 17 5 7 1 Combining GP Timer Co...

Page 323: ..._CMP bit is 0 or themaximum of GP Timer x Maxcount Compare A GPTMRxMAXCMPA register and GP Timer x Maxcount Compare B GPTMRxMAXCMPB register when the ALT_CMP bit is 1 17 5 7 2 2 Case 2 M2 M1 0 and L1...

Page 324: ...Timer 0 15h 3 GP Timer 2 5h 4 GP Timer 0 16h In this example the second value read for GP Timer 2 5h is less than the first value 7997h However because the first value read for GP Timer 0 15h is less...

Page 325: ...this timer is accurate to the precision of the 33 MHz crystal used in the system A microsecond latch register that provides the number of microseconds since the last time that the millisecond register...

Page 326: ...ts the timer interrupt can sometimes be missed causing the interrupt counter to becomes less accurate over time The software timer included on the lanSC520 microcontroller can be used to resolve these...

Page 327: ...CRO ticks 1000 return mics This is all the code necessary to maintain both a 32 bit microsecond and a 32 bit millisecond timebase for an operating system or other timing needs 18 4 1 Configuration Inf...

Page 328: ...Software Timer 18 4 lan SC520 Microcontroller User s Manual...

Page 329: ...st maskable or non maskable on the first time out If software has not cleared an indicator bit by the second time out the watchdog timer always generates a system reset instead The watchdog timer inte...

Page 330: ...er Mnemonic MMCR Offset Address Function Watchdog Timer Control WDTMRCTL CB0h Watchdog timer enable WDT reset enable interrupt flag duration of the WDT time out interval Watchdog Timer Count Low WDTMR...

Page 331: ...the watchdog timer behavior The same keyed sequence is always used for unlocking the watchdog timer control registers 19 4 1 Configuration Information 19 4 1 1 Keyed Sequences All writes to the Watchd...

Page 332: ..._FLG bit asserted by the first time out the watchdog timer causes a system reset instead of an interrupt request regardless of the setting of the WRST_ENB bit 19 4 1 3 System Reset Generation To confi...

Page 333: ...when the timer is programmed with the WRST_ENB bit cleared an interrupt is generated the time out counter is reset and the IRQ_FLG bit in the Watchdog Timer Control WDTMRCTL register is set If the IRQ...

Page 334: ...s disabled Software must enable it by setting the ENB in the Watchdog Timer Control WDTMRCTL register The watchdog timer time out count defaults to the maximum value The WRST_ENB bit is set for genera...

Page 335: ...neral purpose RAM Three interrupt sources separately maskable with corresponding status bits Time of day alarm is programmable to occur from once per second to once per day Periodic interrupts can be...

Page 336: ...y trip voltage In addition to the backup battery monitor function the voltage monitor also provides a power down signal to the RTC This signal is used to isolate the RTC core from the rest of the inte...

Page 337: ...turned off An implementation using a backup battery is shown in Figure 20 3 The primary power source for VCC_RTC is the main power plane VCC D1 should be chosen so that the forward voltage drop is sma...

Page 338: ...ernal diode The on chip voltage monitor circuit monitors the voltage level of the backup battery through the BBATSEN pin each time the PWRGOOD signal is asserted If the backup battery is sampled below...

Page 339: ...ation and detailed specifications for selecting a 32 768 kHz crystal 20 3 3 Using an External RTC When the lanSC520 microcontroller comes out of reset the internal RTC is enabled If the system applica...

Page 340: ...ters Direct Mapped Register Mnemonic I O Address Function RTC CMOS RAM Index RTCIDX 0070h RTC index to read or write RTC CMOS RAM Data Port RTCDATA 0071h Data to be read or written Table 20 3 Real Tim...

Page 341: ...UIP bit there are at least 244 s before the time or calendar data will be changed If a 1 is read in the UIP bit the time or calendar data may not be valid Note that the time allocated to read time or...

Page 342: ...1 3 Generating Periodic Interrupts Different periodic interrupt rates can be specified by programming the RATE_SEL bit field in the RTC Control A RTCCTLA register as shown in Table 20 4 The periodic...

Page 343: ...r must accept four digit years The routine that sets the RTC stores the lower portion of the year value in the RTC Current Year RTCCURYR register and the upper portion in the century CMOS memory locat...

Page 344: ...RTCDATA register Port 0071h or write the desired data byte to this data port 20 5 4 3 Legacy NMI Enable Bit Moved In PC AT compatible systems bit 7 of the write only RTC CMOS RAM Index RTCIDX registe...

Page 345: ...grammed To change the data mode the ten data bytes must be re initialized 20 6 1 RTC Reset The RTC is not automatically reset by a system reset There are three conditions that trigger an RTC reset BBA...

Page 346: ...Real Time Clock 20 12 lan SC520 Microcontroller User s Manual...

Page 347: ...eceiver are each buffered with 16 byte FIFOs Full duplex data can be sent in both directions simultaneously DMA operation Internal baud rate clock of 18 432 MHz or 1 8432 MHz Baud rates from DC to 1 1...

Page 348: ...here are internal pullup resistors on these signals Table 21 1 UART Signals Shared with Other Interfaces PIO Default Function Interface Function Control Bit Register PIO31 RIN2 PIO31_FNC PIO31 PIO16 P...

Page 349: ...Table 21 2 Connection of DTE to DTE DTE DTE SOUT SIN SIN SOUT CTS RTS RTS CTS DSR DTR DTR DSR RIN RIN DCD DCD Table 21 3 UART Registers Memory Mapped Register Mnemonic MMCR Offset Address Function Add...

Page 350: ...T 2 Interrupt ID UART1INTID UART2INTID 02FAh 03FAh FIFO mode indication interrupt identification interrupt pending status UART 1 FIFO Control UART 2 FIFO Control UART1FCR UART2FCR 02FAh 03FAh Trigger...

Page 351: ...ne is always held High between frames idle state Transmission of a frame is initiated when a byte is written to the UART x Transmit Holding UARTxTHR register Reception of a frame is initiated when a s...

Page 352: ...ange DCDx Data Carrier Detect input When the signal is Low it indicates that the data carrier has been detected by the modem and that contact between it and the other modem is established The state of...

Page 353: ...RT frame has been received the character is transferred from the internal receive shift register into the UART x Receive Buffer UARTxRBR register 3 The Data Ready DR bit in the UART x Line Status UART...

Page 354: ...ta input was detected to be 0 for a time longer than a full UART frame including start bit data bits parity and stop bits The character loaded into the FIFO on a break indication is always 0 and subse...

Page 355: ...divisor value in decimal and hexadecimal to use with each clock frequency to achieve common baud rates 21 5 4 2 Hardware Flow Control When the EMSI bit of the UART x Interrupt Enable UARTxINTENB regis...

Page 356: ...haracter For 16550 compatible mode this means that the transmit FIFO is not full 21 5 5 2 Receive DMA The internal rx_dma_req signal from the UART is asserted For 16550 compatible mode whenever the re...

Page 357: ...usly the highest priority interrupt is identified in the INT_ID bit field of the UART x Interrupt ID UARTxINTID register Source Event Polled Status Bit Receive DMA transfer count UART x General Contro...

Page 358: ...terrupt source Note In 16450 compatible mode the INT_ID2 bit always reads back 0 The INT_ID bit field is located in the UART x Interrupt ID UARTxINTID register The UART interrupts are enabled by the I...

Page 359: ...igured by software 1 Configure the UART by programming the desired baud rate character length stop bits and parity 2 Enable interrupts and DMA operation as desired Note that for UART interrupts to pro...

Page 360: ...UART Serial Ports 21 14 lan SC520 Microcontroller User s Manual...

Page 361: ...Programmable SSI clock speed from 64 kHz to 8 MHz Transaction complete status available as interrupt 22 2 BLOCK DIAGRAM A block diagram of the SSI is shown in Figure 22 1 System diagrams as well as ti...

Page 362: ...data to be shifted out to SSI_DO pin SSI Command SSICMD CD2h Transfer command to be executed transmit receive or simultaneous transmit receive SSI Status SSISTA CD3h Busy status transaction complete s...

Page 363: ...receive transaction shifts a byte from SSI_DI to the SSI Receive SSIRCV register MMCR offset CD4h Simultaneously transmit and receive full duplex The lanSC520 microcontroller SSI is always the master...

Page 364: ...nication Non Inverted Phase and Clock Modes SSI_CLK SSI_DO SSI_DI PIOx Data in Data out Enable Clock in Data in Data out Clock in Enable PIOx lan SC520 Microcontroller Four Pin Slave Synchronous Seria...

Page 365: ...bit When the CLK_INV_ENB bit has a value of 0 SSI_CLK idles High then pulses Low during a transaction If the CLK_INV_ENB bit is written to a 1 the clock idle state is Low 22 5 2 3 Clock Phase The cloc...

Page 366: ...d 3 The last four bits on SSI_DO can specify a four bit NOP command if they are not ignored by the slave 4 The first four bits on SSI_DI are shifted in but can be ignored by software 5 The last four b...

Page 367: ...errupts An interrupt can be generated by the SSI to alert the CPU that a transaction is complete 1 The interrupt is enabled by writing the TC_INT_ENB bit to a 1 in the SSI Control SSICTL register 2 Wh...

Page 368: ...n SSI command is executed Some or all of the following steps should be taken to initiate an SSI transaction 1 Enable disable CPU transaction complete interrupt via the TC_INT_ENB bit in the SSI Contro...

Page 369: ...e g GP bus signals This is done to give system designers the most flexibility For clarity throughout this document the two functions available on the PIO pins are distinguished from each other as the...

Page 370: ...ame pin Note All PIOs are terminated by either pullup or pulldown resistors depending on interface function s needs The pullup and pulldown resistors are approximately 100 150 ohms The termination of...

Page 371: ...t with pullup PIO24_FNC PIO23 GPIRQ0 input with pullup PIO23_FNC PIO22 GPIRQ1 input with pullup PIO22_FNC PIO21 GPIRQ2 input with pullup PIO21_FNC PIO20 GPIRQ3 input with pullup PIO20_FNC PIO19 GPIRQ4...

Page 372: ...DY GPBHE GPALE PIO31 PIO16 Pin Function Select PIOPFS31_16 C22h PIO31 PIO16 orinterface function select RIN2 DCD2 DSR2 CTS2 GPCS0 GPMEMCS16 GPIOCS16 GPDBUFOE GPIRQ7 GPIRQ0 Chip Select Pin Function Sel...

Page 373: ...X Not used in this operation X X X 3 3 Input value The Data register bit state always reflects the corresponding pin state whether input or output The pin is not a PIO it uses its interface function T...

Page 374: ...cess the bus 23 6 INITIALIZATION After a system reset all of the PIO31 PIO0 signals default to be inputs with pullup or pulldown resistive termination The signals must be programmed before using them...

Page 375: ...data on the GP bus during Am5x86 CPU accesses of internal integrated peripherals Disabling the Am5x86 CPU s integrated cache controller controlling the cache write policy and specifying noncacheable...

Page 376: ...Mnemonic MMCR Offset Address Function Am5x86 CPU Control CPUCTL 02h CPU cache mode select write through or write back CPU clock speed SDRAM Control DRCCTL 10h Systemtestmode CF_DRAM DATASTRB and CF_RO...

Page 377: ...o provided to identify when the data on the SDRAM data bus is valid This signal is used primarily by in circuit emulation tools for capturing SDRAM data when monitoring this interface System test mode...

Page 378: ...GP bus interfaces including when the Am5x86 CPU is the initiator when the data is valid during SDRAM read and write cycles and differentiating between code fetches and data accesses This still requir...

Page 379: ...the SDRAM Timing Control DRCTMCTL register MMCR offset 12h The BA1 BA0 and MA12 MA0 bus can be used to determine the physical address generated by the requesting master Figure 24 2 System Test Mode T...

Page 380: ...not permitted to initiate cycles on the GP bus The signals required to trace cycles on the GP bus will vary depending on the type of slave devices connected externally Note that due to performance li...

Page 381: ...ster GP DMA controller or a combination of these has written into a particular rank of the write buffer 24 4 2 1 Using the Write Buffer Test Mode Interface Sampling the WBMSTR2 WBMSTR0 pins for write...

Page 382: ...though more than one of these sources may have written to a given rank in the write buffer only one initiator can read a rank at any given time Table 24 4 describes the WBMSTR2 WBMSTR0 pins during a S...

Page 383: ...ured on the rising edge of CLKMEMIN The CAS latency timing is configured in the SDRAM Timing Control DRCTMCTL register MMCR offset 12h The MA12 MA0 and BA1 BA0 signals can be used to determine the phy...

Page 384: ...the GP bus using GP bus echo mode If required a logic analyzer can be connected to the GP bus to monitor and debug the transactions When the GP_ECHO_ENB bit is set in the GP Echo Mode GPECHO register...

Page 385: ...Software Considerations The cache should always be flushed after the cacheability attribute for an address range is changed from cacheable to noncacheable for any memory region by programming a PAR r...

Page 386: ...o predict the exact effect of these buffers on each system because there are many dependencies However it should be noted that in some cases a notable change in system performance will occur This also...

Page 387: ...n correctly Interconnections between various components are correct Various components interact correctly on the printed circuit board 25 2 BLOCK DIAGRAM Figure 25 1 shows a block diagram of the Bound...

Page 388: ...nd the test data register to be accessed Test Data Registers Boundary Scan BSR register Device Identification DID register Bypass BPR register and Serial Debug Port Data SDPD register Test Access Port...

Page 389: ...n the microcontroller s input pins to be loaded into their corresponding Boundary Scan register locations I O pins are selected as input or output depending on the value loaded into their control sett...

Page 390: ...llup resistor on the JTAG_TDI input This has been done to prevent any unwanted interference with the proper operation of the system logic The Instruction register can be accessed when this command is...

Page 391: ...te Each of the shaded control cells shown in Table 25 3 contains the output enable control for the pads listed below the control cell and before the next control cell For bidirectional pads the output...

Page 392: ...irectional 70 71 MD4 Bidirectional 72 73 MD3 Bidirectional 74 75 MD2 Bidirectional 76 77 MD1 Bidirectional 78 79 MD0 Bidirectional 80 81 MECC6 Bidirectional 82 83 MECC5 Bidirectional 84 85 MECC4 Bidir...

Page 393: ...33 134 AD29 Bidirectional 135 136 AD28 Bidirectional 137 138 AD27 Bidirectional 139 140 AD26 Bidirectional 141 142 AD25 Bidirectional 143 144 AD24 Bidirectional 145 146 AD23 Bidirectional 147 148 AD22...

Page 394: ...Bidirectional 200 201 CBE0 Bidirectional 202 203 Control 204 PAR Bidirectional 205 206 SERR Input 207 Control 208 PERR Bidirectional 209 210 Control 211 FRAME Bidirectional 212 213 Control 214 TRDY B...

Page 395: ...rectional 259 260 GPA20 Bidirectional 261 262 GPA19 Bidirectional 263 264 GPA18 Bidirectional 265 266 GPA17 Bidirectional 267 268 GPA16 Bidirectional 269 270 GPA15 Bidirectional 271 272 GPA14 Output 2...

Page 396: ...D1 Bidirectional 318 319 GPD0 Bidirectional 320 321 Control 322 GPRESET Output 323 Control 324 GPIORD Output 325 Control 326 GPIOWR Output 327 Control 328 GPMEMRD Output 329 Control 330 GPMEMWR Output...

Page 397: ...ol 380 PIO11 Bidirectional 381 382 Control 383 PIO10 Bidirectional 384 385 Control 386 PIO9 Bidirectional 387 388 Control 389 PIO8 Bidirectional 390 391 Control 392 PIO7 Bidirectional 393 394 Control...

Page 398: ...irectional 436 437 Control 438 DTR2 Output 439 Control 440 PIO30 Bidirectional 441 442 Control 443 PIO31 Bidirectional 444 445 Control 446 SSI_CLK Output 447 SSI_DI Input 448 Control 449 SSI_DO Output...

Page 399: ...ure 25 2 Serial Debug Port Data Register Format 25 4 2 5 Device Identification Register Figure 25 3 shows the format of the Device Identification register For the lanSC520 microcontroller the least si...

Page 400: ...uence of operations of the test logic The TAP controller changes state in response to the rising edge of JTAG_TCK It can be reset to the Test Logic Reset state either by holding the JTAG_TRST pin Low...

Page 401: ...S is High The TAP controller is also forced to enter this state when JTAG_TRST is asserted The JTAG TAP controller is not reset as a function of PWRGOOD when the system is powered up Rather JTAG_TRST...

Page 402: ...een JTAG_TDI and JTAG_TDO as a result of the current instruction shifts data one stage toward its serial output on each rising edge of JTAG_TCK The instruction does not change in this state When the T...

Page 403: ...held Low 25 4 3 1 10 Select Instruction Register IR Scan State This is a temporary controller state The test data register selected by the current instruction retains its previous state If JTAG_TMS i...

Page 404: ...he Exit2 IR state 25 4 3 1 15 Exit2 IR State This is a temporary state While in this state if JTAG_TMS is held High a rising edge applied to JTAG_TCK causes the controller to enter the Update IR state...

Page 405: ...er Parallel Output of IR Data Input to BSR BSR Shift Register Parallel Output of BSR Register Selected JTAG_TDO Enable JTAG_TDO Select DR Scan Run Test Idle Capture DR Shift DR Exit1 DR Pause DR Exit2...

Page 406: ...ler leaves the reset state owing to an erroneous Low 0 signal on the JTAG_TMS line at the time of a rising edge on JTAG_TCK it returns to the reset state after JTAG_TMS is held High for three rising e...

Page 407: ...echnology uses a serial connection based on an enhanced JTAG protocol and an inexpensive 12 pin connector that can be placed on each board design This low cost solution satisfies the requirement of a...

Page 408: ...JTAG_TDI and JTAG_TDO Using JTAG pins alone without the advantages of additional support pins the lowest possible cost is achieved in terms of processor pins but with the cost of reduced functionalit...

Page 409: ..._TDI Input PU Input test data and instructions JTAG_TDO Output PU Output data three stated when data is not driven JTAG_TMS Input PU Test functions and sequence of test changes JTAG_TRST Input PU Rese...

Page 410: ...should support a ribbon cable equipped with a female connector for attaching to the target The appropriate last pin pin 12 or pin 20 should not be installed or if necessary removed at this location At...

Page 411: ...G to support AMDebug technology When AMDebug technology debugging is not used the jumpers can be set to connect the processor with the other devices forming the scan chain Figure 26 5 Locating the Tar...

Page 412: ...me data that is gathered in the on chip trace cache described in Section 26 4 1 except that now trace depth is limited by the external hardware rather than the depth of the on chip trace cache provide...

Page 413: ...ue is placed in the trace cache This scheme does not have all of the capabilities offered by a system assisted by external off chip hardware however no instrumentation of code is required before profi...

Page 414: ...AMDebug Technology 26 8 lan SC520 Microcontroller User s Manual...

Page 415: ...4 11 I O space 4 10 Configuration Base Address register 4 11 GP bus I O region 4 14 PC AT compatible I O peripherals region 4 12 PCI configuration space 4 11 PCI I O space 4 12 initialization 4 20 in...

Page 416: ...usage 8 8 8 20 8 22 arbitration See system arbitration ARBPRICTL register 8 2 ATTR bit field 3 10 3 12 4 5 4 15 B BA1 BA0 signals control 10 10 10 19 description 2 5 Backup Battery Sense signal See B...

Page 417: ..._NUM 9 10 RF_CLR 21 10 RFRT 21 7 21 10 RFSH_ENB 10 19 RFSH_SPD 10 18 RTC_DIS 3 21 20 5 RTC_VRT 6 7 20 4 RTG 17 3 S1_GINT_MODE 15 18 S2 15 17 15 18 15 19 bit fields continued S2_GINT_MODE 3 19 S5 15 17...

Page 418: ...ister function 12 5 13 6 16 2 17 2 23 4 usage 12 3 13 3 13 22 16 1 17 1 23 5 chip selects See GPCS7 GPCS0 signals Class Code Revision ID PCICCREVID register function 9 8 Clear To Send signals See CTS2...

Page 419: ...6 4 6 7 CPUCTL register 7 1 CSPFS register 23 4 CTR_MODE bit field 16 4 CTS2 CTS1 signals control 13 6 21 2 21 3 21 4 description 2 9 21 6 usage 21 2 21 9 customer service iii D data buses boot devic...

Page 420: ...atus ECCSTA register function 10 10 usage 10 27 ECC See SDRAM controller ECC_CHK_POS bit field 10 28 ECCCKBPOS register 10 10 ECCCKTEST register 10 10 ECCCTL register 10 10 ECCMAP register 15 4 ECCMBA...

Page 421: ...ss Region x PARx registers 3 8 data sizing 13 9 DMA interface 13 11 echo mode 13 8 13 10 echo mode minimum timing table 13 9 GP bus reset 6 7 I O space 4 14 I O mapped device support 13 9 initializati...

Page 422: ...s Memory Chip Select 16 signal See GPMEMCS16 signal GP Bus Memory Read signal See GPMEMRD signal GP Bus Memory Write signal See GPMEMWR signal GP Bus Ready signal See GPRDY signal GP Bus Reset signal...

Page 423: ...function 14 6 usage 14 15 14 18 GP DMA Channel x Next Transfer Count Low GPDMANXTTCLx register function 14 6 usage 14 15 14 18 GP DMA Control GPDMACTL register function 5 6 14 4 usage 5 8 14 10 14 18...

Page 424: ...13 6 14 4 description 2 8 usage 14 3 14 10 GPECHO register 13 5 GPIOCS16 signal control 13 3 13 6 description 2 8 timing 13 19 usage 13 4 13 10 13 11 24 6 GPIORD signal control 13 5 description 2 8 us...

Page 425: ...host bridge 9 29 power on reset 6 9 programmable input output PIO 23 6 programmable interrupt controller PIC 15 20 programmable interval timer PIT 16 7 read buffer 11 15 real time clock RTC 20 10 res...

Page 426: ...2 JTAG_TDI signal description 2 12 usage 25 2 25 4 26 2 JTAG_TDO signal description 2 12 usage 25 2 25 3 25 4 26 2 JTAG_TMS signal usage 2 12 25 14 26 2 JTAG_TRST signal description 2 12 usage 25 14...

Page 427: ...uest MSTDMASWREQ register function 14 7 MATCH bit field 4 17 MBIT_ERR bit field 10 27 MD31 MD0 signals control 10 10 10 19 23 4 description 2 5 2 6 usage 10 6 10 9 24 4 24 6 MECC6 MECC0 signals contro...

Page 428: ...figuration Data PCICFGDATA register function 9 8 usage 4 11 9 9 9 10 9 11 9 17 PCI host bridge arbitration 8 3 block diagram figure 9 2 broken transactions 8 19 bus arbitration 8 3 configuration 9 9 g...

Page 429: ...15 4 pins See signals pinstraps signal descriptions 2 13 PIO functions See programmable input output PIO PIO15 PIO0 Clear PIOCLR15_0 register function 23 4 usage 23 5 PIO15 PIO0 Data PIODATA15_0 regis...

Page 430: ...ng pages and regions 3 9 start address 4 18 usage 2 11 3 8 3 10 4 5 12 14 13 6 13 9 13 22 15 9 worksheet figure 3 11 write protection 3 12 programmable input output PIO block diagram figure 23 2 confi...

Page 431: ...2 PWRGOOD signal description 2 10 timing 6 9 usage 6 2 6 4 6 8 20 5 PWRGOOD_DET bit field 6 8 R RAS_CAS_DLY bit field 10 21 RAS_PCHG_DLY bit field 10 21 RATE_SEL bit field 20 8 read buffer See write...

Page 432: ...MANXTTCHx 14 6 GP DMA Channel x Next Transfer Count Low GPDMANXTTCLx 14 6 GP DMA Control GPDMACTL 14 4 GP DMA Memory Mapped I O GPDMAMMIO 14 4 GP DMA Resource Channel Map A GPDMAEXTCHMAPA 14 4 registe...

Page 433: ...7 RTC Status D RTCSTAD 20 7 RTC CMOS RAM Data Port RTCDATA 20 6 RTC CMOS RAM Index RTCIDX 20 6 SCP Command Port SCPCMD 6 3 SCP Data Port SCPDATA 6 3 registers continued SDRAM Bank 0 3 Ending Address...

Page 434: ...after system reset table 6 5 determining reset sources 6 8 GP bus reset 6 7 hard CPU reset 7 5 initialization 6 9 latency 6 9 operation 6 3 overview 6 1 PCI reset 6 7 PLL start up 6 8 PLL start up ti...

Page 435: ...CS1 signals control 3 10 12 3 13 3 13 6 description 2 6 usage 3 17 4 8 4 14 12 3 12 14 24 6 ROMRD signal description 2 6 usage 12 3 24 4 24 6 Row Address Strobe signals See SRASA SRASB signals RST sig...

Page 436: ...CCFG register function 10 10 usage 10 15 10 33 SDRAM Buffer Control DBCTL register function 11 4 24 2 usage 11 5 11 9 11 13 24 10 SDRAM Chip Select signals See SCS3 SCS0 signals SDRAM Clock Input sign...

Page 437: ...0 10 usage 10 20 10 31 24 5 24 9 Serial Data In signals See SIN2 SIN1 signals Serial Data Out signals See SOUT2 SOUT1 signals Serial Debug Port Data SDPD register format 25 13 function 25 2 usage 25 1...

Page 438: ...BMSTR0 2 13 SIN2 SIN1 signals description 2 9 usage 21 2 Slave DMA Channel 0 3 Control SLDMACTL register function 14 7 Slave DMA Channel 0 3 Mask SLDMAMSK register function 14 7 Slave DMA Channel 0 3...

Page 439: ...4 usage 15 8 software timer block diagram figure 18 1 configuration 18 2 initialization 18 3 operation 18 2 overview 18 1 registers 18 2 Software Timer Configuration SWTMRCFG register function 5 6 18...

Page 440: ...2 5 clock idle state 22 5 clock phase 22 5 initialization 22 8 interrupts 22 7 operation 22 3 overview 22 1 registers 22 2 signal descriptions 2 9 software considerations 22 8 system design 22 1 four...

Page 441: ...12 code execution control 3 12 external GP bus devices 3 13 external ROM devices 3 17 format figure 3 10 PAR register priority 3 13 PCI bus devices 3 15 performance considerations of attributes 3 12 S...

Page 442: ...ation 21 9 baud rate 21 9 hardware flow control 21 9 operating modes 21 9 data reception 21 7 data transmission 21 6 disabling 3 21 DMA interface 21 10 receive DMA 21 10 transmit DMA 21 10 UART as GP...

Page 443: ...usage 5 3 20 4 VCC_CORE signal description 2 14 VCC_I O signal description 2 14 VCC_RTC signal usage 2 10 2 14 6 9 20 3 20 4 20 11 W watchdog timer WDT AMDebug technology interface 19 5 block diagram...

Page 444: ...3 system design 11 3 shared signals table 11 4 write buffer 11 5 disabled 11 5 enabled 11 5 read merging 11 8 read merging example figure 11 9 watermark 11 9 write collapsing 11 6 write collapsing exa...

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