AMD Elan SC520, User Manual, Page: 210 / 444

SDRAM Controller
10-32 Élan™SC520 Microcontroller User’s Manual
10.6.3 Boot Process
In a closed embedded system, the designer may be able to simply choose the correct
values to output to the configuration registers. Systems where the SDRAM parameters are
not known at boot time present more issues. Many SDRAM considerations, such as signal
loading, cannot be accurately determined by software. One way to deal with this issue is
to have a staged boot process, as follows:
1. First, all timing registers are programmed to assume a worst-case system by default
after reset.
2. Next, the SDRAM banks are tested for SDRAM existence, organization, and size. Banks
that contain SDRAM are enabled with the correct parameters.
3. A system memory test is then performed to ensure that there are no problems. The user
can be notified, and bad banks can be disabled, if any problems are encountered.
Since the user has control over SDRAM setup parameters, they must not be applied to the
SDRAM array until late in the boot process, so that the setup program can always be used
to recover the system if it becomes unbootable.
10.6.4 SDRAM Sizing Algorithm
The SDRAM sizing algorithm must alter the SDRAM configuration registers and write and
read specific boundary SDRAM locations to determine where the SDRAM bank boundary
exists. Data that is written and then returned on a read implies that valid SDRAM exists at
that location.
However, prior to accessing the SDRAM devices, the mode register for the device must be
programmed to configure the devices before they are functional. SDRAM device
initialization is discussed in more detail in Section 10.6.2. Note that SDRAM refresh cycles
should only be enabled when the OPMODE_SEL bit field is configured for normal SDRAM
mode. After the SDRAM devices are initialized (with refresh cycles remaining disabled),
they can be reliably accessed.
The SDRAM controller provides many configuration registers with control and timing
configuration functions. However, only a subset of these registers is required to be accessed
during the sizing procedure. In particular, the bits associated with specifying the column
address width, the internal bank count specifier, and the bank ending address are the most
critical for the sizing process.
■ The column address width is used to specify the column width of the device.
■
The internal bank count bit specifies if the device supports either two or four internal
banks.
■
The SDRAM Bank 0–3 Ending Address (DRCBENDADR) register (MMCR offset 18h)
is used to specify the physical address bank boundary.
The column boundary method is used to accept a wide variety of SDRAM devices and
symmetries. In configuring the symmetry of the device, this method requires only the column
address width to be specified. Device addressing and symmetries are discussed in “SDRAM
Addressing” on page 10-12.
It is important to point out that whenever the column address width, internal bank count, or
bank ending address configuration is going to be changed, the All Banks Precharge
command must be issued prior to the configuration update. The All Banks Precharge
command can be enabled with a binary pattern of 010b being written to the OPMODE_SEL
bit field. A cycle to SDRAM must be run for the command to take effect. The All Banks