AMD Elan SC520, User Manual, Page: 208 / 444

SDRAM Controller
10-30 Élan™SC520 Microcontroller User’s Manual
to occur throughout the entire duration of the programmable reset. Upon the assertion of
the programmable reset, the SDRAM controller arbiter lets the current SDRAM access
complete before returning the controller state machines to their idle states. This prevents
data corruption in the SDRAM array should the programmable reset be asserted
during an
access to SDRAM. All SDRAM controller configuration is maintained.
Note: The contents of the write buffer are discarded for both types of reset. Also, the enable
states of the write buffer and read buffer are not maintained after a programmable reset.
Therefore, if the write buffer and read buffer were enabled prior to the programmable reset,
software must re-enable them after the programmable reset.
10.6.2 SDRAM Device Initialization
Section 10.6.2– Section 10.6.4 provide details on enabling the core and SDRAM
configuration. However, prior to altering the SDRAM configuration, the write buffer and
read-ahead feature of the read buffer must be disabled. This is to prevent SDRAM
configuration changes while a write buffer or read-ahead prefetch to SDRAM is in progress.
Refresh should be disabled anytime the SDRAM controller is not operating in normal
SDRAM mode. SDRAM refresh cycles should only be enabled when the OPMODE_SEL
bit field is configured for normal SDRAM mode. After the SDRAM devices are initialized
(with refresh cycles remaining disabled), they can be reliably accessed.
If the Error Correction Code (ECC) logic for SDRAM is enabled, the ECC operation requires
that SDRAM and its associated ECC memory be initialized. This is accomplished by the
boot code that must write to every location in SDRAM. This process initializes the ECC
SDRAM to reflect the proper Hamming code for its associated data. If this procedure is not
performed, false errors will occur when reading or when writing data smaller than a 32-bit
doubleword. See “Error Correction Code (ECC)” on page 10-16 for a more detailed
discussion of ECC.
10.6.2.1 Operation Mode Select
SDRAM devices must be powered up and initialized in a predefined manner prior to access.
The SDRAM controller’s SDRAM Control (DRCCTL) register (MMCR offset 10h) provides
support for this procedure via the OPMODE_SEL field.
■ By default, the OPMODE_SEL bit field reflects a normal SDRAM mode of operation.
However, a
normal SDRAM mode of operation refers to the mode the SDRAM controller
must be configured in after SDRAM device initialization is complete. Normal SDRAM
mode allows read and write accesses to occur as requested by a master. SDRAM refresh
cycles should be enabled only when the OPMODE_SEL field is configured for normal
SDRAM mode.
■ The other settings for the OPMODE_SEL field force all SDRAM accesses to a specific
SDRAM command type: NOP, Precharge, Load Command, or Refresh. Setting the
OPMODE_SEL bits to
non-normal SDRAM mode results in all banks being selected
(i.e., SCS3–SCS0 are driven active), so that the command is applied to all SDRAM
devices in the system.
To generate the command specified in the OPMODE_SEL field, an Am5
x
86 CPU read or
write cycle must be generated to the SDRAM region. The specified command occurs at
the SDRAM interface rather than the actual read or write cycle requested by the Am5
x
86
CPU.