AMD Elan SC520, User Manual, Page: 194 / 444

SDRAM Controller
10-16 Élan™SC520 Microcontroller User’s Manual
10.5.2.2 Page Size
The page size of an SDRAM device is based on the column address width of the device.
The ÉlanSC520 microcontroller address mapping takes advantage of the full page specified
by the devices column address width. Table 10-10 lists the page size available based on
the column address width specified. The page size in an SDRAM device applies for each
internal bank.
10.5.3 Error Correction Code (ECC)
The ÉlanSC520 microcontroller supports Error Correction Code (ECC) to check the integrity
of transactions with the system SDRAM. ECC is implemented by a modified Hamming
code. It corrects a single-bit error and detects all two-bit (called
multi-bit) errors. The memory
array must have check bits to implement ECC.
ECC operation requires that system memory be initialized. In this procedure, the boot code
writes to every memory location, automatically generating valid ECC that is stored in the
SDRAM check bits. If this procedure is not performed, errors will occur in the generation
of the check bits when writing data smaller than a 32-bit doubleword or when reading un-
initialized data.
The ECC circuit uses a modified Hamming code to generate a 7-bit check word from the
32-bit data word. This check word is stored along with the data word during the memory
write cycle. During the memory read cycle, the 39-bit words from memory are processed
by the ECC circuit to determine if errors have occurred in storing or retrieving data.
If there is a single-bit error in the 32-bit data word or check-bits, the ECC circuit flags an
error, latches the error-generating address along with the bit position where the error was
detected, and passes along the corrected data word to the requesting master. It does not
write the corrected data back out to the SDRAM. It generates a maskable interrupt signal
when a single-bit error is detected. This maskable interrupt signal is generated even if there
is a single-bit error in the 7-bit check word.
Multi-bit errors are flagged but not corrected. These errors may occur in any two bits of the
39-bit word from memory (two errors in the 32-bit data word, two errors in the 7-bit check
word, or one error in each word). A separate non-maskable interrupt is generated by the
ECC logic for multi-bit errors.
These two interrupts are routed to the interrupt steering logic in the programmable interrupt
controller. See Chapter 15, “Programmable Interrupt Controller”, for more details and
further options.
If there is any write that is less than the full four bytes, there is a loss of performance due
to ECC. The seven check-bits for any given ECC data field are generated over the entire
field. In other words, all four bytes of data are taken into account in generating the seven
check-bits associated with that data. If any changes were to occur to any of the data bytes,
the check-bits would no longer be correct.
Table 10-10 SDRAM Page Sizes
Column Width Page Size for 32-Bit Banks
8-bit 1 Kbyte
9-bit 2 Kbytes
10-bit 4 Kbytes
11-bit 8 Kbytes