AMD Elan SC520, User Manual, Page: 289 / 444

Élan™SC520 Microcontroller User’s Manual 15-1
CHAPTER
15
PROGRAMMABLE INTERRUPT
CONTROLLER
15.1 OVERVIEW
The ÉlanSC520 microcontroller’s programmable interrupt controller (PIC) consists of three
industry-standard controllers, integrated with a highly programmable interrupt router.
The programmable interrupt controller is configured so that two controllers are cascaded
as slaves to a master controller that arbitrates interrupt requests from various sources to
the Am5
x
86 CPU. Interrupt channel 2 (IR2) and channel 5 (IR5) of the Master controller
are hard-wired to the outputs of the Slave 1 and Slave 2 controller respectively. In this
configuration, up to 22 maskable interrupt channels of different priorities are available to
the programmer.
The programmable interrupt router handles routing of the various external and internal
interrupt sources to the 22 interrupt channels of the three controllers. The interrupt router
can also be programmed to handle routing of various NMI sources to generate a non-
maskable interrupt to the CPU.
The ÉlanSC520 microcontroller’s programmable interrupt controller is designed to support
PC/AT-compatible features. Startup software can configure the programmable interrupt
router to route the sources to be used as ISA interrupts to the appropriate interrupt channels
of the Slave 1 and Master controllers.
PCI interrupts are level-sensitive, shareable, and typically implemented as open-drain
inputs. To support this, the programmable interrupt controller optionally allows the selection
of edge-triggered or level-sensitive interrupt detection on a per-channel basis, as an
alternative to the standard global selection of edge-triggered or level-sensitive detection
on all channels. This enhancement provides maximum flexibility in configuring a system
environment where mixed interrupt types are used.
Features of the ÉlanSC520 microcontroller’s programmable interrupt controller include:
■ 22 interrupt priority levels plus NMI
■
Programmable interrupt router capable of mapping interrupt sources (internal and
external) to different priorities or NMI
■
15 general-purpose external interrupt requests (GPIRQ10–GPIRQ0 and INTA–INTD),
programmable to be edge- or level-sensitive
■
19 internal interrupt requests programmable to be edge- or level-sensitive
■ Ability to assert any of the interrupt priority levels, including NMI, via software
■
Configurable to provide software compatibility with PC/AT interrupt controller
■ Programmable interrupt polarity inversion for external sources
■ Am5
x
86 CPU floating point error (ferr) interrupt clear, ignne function