AMD Elan SC520, User Manual, Page: 166 / 444

PCI Bus Host Bridge
9-18 Élan™SC520 Microcontroller User’s Manual
to the PCI Configuration Data (PCICFGDATA) register that access external PCI bus device
configuration registers.
Figure 9-13 CPU Read Cycles from Internal PCI Bus Configuration Registers
9.5.4 Élan™SC520 Microcontroller’s Host Bridge as PCI Bus Target
As a target, the integrated PCI host bridge only accepts memory cycles from external PCI
bus masters to allow accesses to the ÉlanSC520 microcontroller’s SDRAM.
To enable the host bridge as a PCI bus target device, the Memory Access Enable
(MEM_ENB) bit in the Status/Command (PCISTACMD) register must be set. When this bit
is set, the PCI host bridge ignores all I/O and configuration cycles on the PCI bus and
responds to memory cycles within the address space, as defined in Section 9.5.4.1.
9.5.4.1 PCI Host Bridge Target Address Space
Under normal conditions, the ÉlanSC520 microcontroller’s PCI host bridge responds to PCI
bus master memory cycles in the entire SDRAM address space to allow full access of
SDRAM from external PCI bus masters. This space is defined as a linear region, starting
at the lowest address (00000000h) and ending at the top of SDRAM, depending on the
amount populated in the system (a maximum of 256 Mbytes). The SDRAM controller’s
configuration registers are programmed with the amount of SDRAM in the system during
the initial boot process.
Some systems may require specific CPU address space that is normally defined as an
SDRAM region to be redirected to the PCI bus. An example application is a PCI-bus-based
VGA video card for PC/AT compatibility. In ÉlanSC520 microcontroller, this redirection is
programmed via the first two Programmable Address Region (PAR) registers (PAR 0 and
PAR 1). When this feature is used in a system, the ÉlanSC520 microcontroller’s PCI host
bridge target shadows PAR 0 and PAR 1 and ignores accesses by external PCI bus masters
in the programmed address space if they are programmed for PCI bus in the TARGET field.
See Chapter 4, “System Address Mapping”, for further details of PCI host bridge target
address space.
Because the ÉlanSC520 microcontroller is configured as a PCI host bridge, the PCI bus
Base Address registers normally found in the PCI bus configuration space are not
implemented.
1 2 3 4
read data
clk_cpu
ads
cycle_info
rdy
Data