AMD Elan SC520, User Manual, Page: 33 / 444

Architectural Overview
Élan™SC520 Microcontroller User’s Manual 1-5
1.3.3 Industry-Standard PCI Bus Interface (Chapter 9)
The ÉlanSC520 microcontroller provides a 33-MHz, 32-bit PCI bus Revision 2.2-compliant
host bridge interface, including integrated write-posting and read-buffering capabilities
suitable for high-throughput applications. The PCI host bridge leverages standard
peripherals and software. It also provides:
■ High throughput (132 Mbytes/s peak transfer rate)
■
Deep buffering and support for burst transactions from PCI bus masters to SDRAM
■ Flexible arbitration mechanism
■
Support for up to five external PCI masters
1.3.4 High-Performance SDRAM Controller (Chapter 10)
The ÉlanSC520 microcontroller provides an integrated SDRAM controller that supports
popular industry-standard synchronous DRAMs (SDRAM).
■ The SDRAM controller interfaces with SDRAM chips as well as with most standard
DIMMs to enable use of standard off-the-shelf memory components.
■ The SDRAM controller supports programmable timing options and provides the required
external clock.
■ Up to four 32-bit banks of SDRAM are supported with a maximum capacity of 256
Mbytes.
■ An important reliability-enhancing Error Correction Code (ECC) feature is built into the
SDRAM controller. The resultant increase in the memory content reliability enables the
ÉlanSC520 microcontroller to be effectively utilized in applications that require more
reliable operation, such as communications environments.
■ The SDRAM controller contains a write buffer and read ahead buffer subsystem that
improves both write and read performance.
■ SDRAM refresh options allow the SDRAM contents to be maintained during reset.
1.3.5 ROM/Flash Controller (Chapter 12)
The ÉlanSC520 microcontroller provides an integrated ROM controller for glueless
interfacing to ROM and Flash devices. The ÉlanSC520 microcontroller supports two types
of interfaces to such devices—a simple interface via the GP bus for 8- and 16-bit devices,
and an interface to the SDRAM memory data bus for higher performance 8-, 16-, and 32-
bit devices.
The ROM/Flash controller:
■
Reduces system cost by gluelessly interfacing static memory with up to three ROM/
Flash chip selects
■
Supports execute-in-place (XIP) operating systems for applications that require
executing out of ROM or Flash memory instead of DRAM
■
Supports high-performance page-mode devices
1.3.6 Flexible Address-Mapping (Chapter 4)
In addition to the memory management unit (MMU) within the Am5
x
86 CPU core, the
ÉlanSC520 microcontroller provides 16 Programmable Address Region (PAR) registers
that enable flexible placement of memory (SDRAM, ROM, Flash, SRAM, etc.) and
peripherals into the two address spaces of the Am5
x
86 CPU (memory address space and