AMD Elan SC520, User Manual, Page: 255 / 444

General-Purpose Bus Controller
Élan™SC520 Microcontroller User’s Manual 13-11
Note that accesses initiated by the GP bus DMA controller are not affected by enabling the
GP bus echo mode, and therefore the GP bus DMA controller still asserts GPAEN as it
does during normal operation.During an internal GPDMA access in GP bus echo mode,
the external GP bus commands, GPIORD, GPMEMRD, GPIOWR, GPMEMWR, are not
asserted. However, GPAEN is still asserted.
While GP bus echo mode is enabled, there are additional restrictions to the programmable
timing parameters that must be taken into account. These are described in “Using GP Bus
Echo Mode with Programmable Timing” on page 13-8.
13.5.7 DMA Interface
There are four DMA channels for external GP bus peripherals. The GPDRQ3–GPDRQ0
signals go directly to the GP-DMA controller, and their levels are programmable in the GP-
DMA controller. All GP-DMA control signals and timing are generated by the GP-DMA
controller, and the programmable timing in the GP bus controller does not affect the GP-
DMA cycle timing. For more information, see Chapter 14, “GP Bus DMA Controller”.
13.5.8 Usage Scenarios
13.5.8.1 Compatibility with Common ISA Devices
The GP bus is compatible with most ISA devices, but the following ISA bus features are
not supported.
■ LA23–LA17 is supported through GPA23–GPA17, but note that because the Am5
x
86
CPU itself does not support address pipelining, address pipelining is not supported on
the GP bus.
■
GPA25–GPA24 is added to increase the GP bus address space up to 64 Mbytes, instead
of 16 Mbytes.
■
External master access is not supported, and the ÉlanSC520 microcontroller is always
the master on the GP bus (external masters can be accommodated by the PCI bus).
■
GPIOCS16 and GPMEMCS16 do not cause the GP bus timings to change for the bus
cycles during which these signals are asserted.
■
IOCHRDY is supported via the GPRDY pin only as an input for the slave devices that
require wait states. GPRDY as an output is not supported, since there is no external
master support.
■ IOCHK is not supported, but a GPIRQx signal (mappable to a maskable or non-maskable
interrupt) can be used to report errors.
■ The REFRESH pin is not supported, because the SDRAM refresh is not echoed out to
the GP bus.
■ NOWS is not supported, due to the programmable interface timing on the GP bus.
■
BCLK and OSC are not supported, because a typical ISA interface is asynchronous.
External oscillators can be used, if needed.
■
The GP bus provides programmable bus interface timing that can be configured to
support most ISA bus devices. However, the GP bus does not support all legacy ISA
timing. See the
Élan™SC520 Microcontroller Data Sheet, order #22003, for information
on the GP bus and GP-DMA timing supported by the ÉlanSC520 microcontroller.
Table 13-4 shows the cross-reference table of the ISA signals and the GP bus signals.