AMD Elan SC520, User Manual, Page: 116 / 444

Reset Generation
6-8 Élan™SC520 Microcontroller User’s Manual
6.5.7 Determining Reset Sources
Status bits are available in the Reset Status (RESSTA) register (MMCR offset D74h) for
software to determine the source of reset. These bits are set when the associated event is
detected and cleared by writing a 1. They include:
■
ICE_HRST_DET—Hard CPU reset from AMDebug logic
■ ICE_SRST_DET—AMDebug system reset
■
WDT_RST_DET—Watchdog timer time-out system reset
■ SD_RST_DET—Soft CPU reset resulting from a detection of the CPU shutdown cycle
due to triple fault
■ PRGRST_DET—System reset from PRGRESET pin that resets the ÉlanSC520
microcontroller, allows SDRAM refresh, and maintains SDRAM configuration
■ PWRGOOD_DET—System reset from PWRGOOD pin
6.5.8 CPU A20 Gate Support
The ÉlanSC520 microcontroller does not support an a20 gate input pin. In a typical PC/AT
system, this input was driven by the external System Control Processor (SCP) in response
to a command request that is issued by the main CPU. In the ÉlanSC520 microcontroller,
this a20 gate command sequence is detected by internal logic, and the appropriate action
is taken.The ÉlanSC520 microcontroller provides an additional a20 gate source in the
System Control Port A (SYSCTLA) register (Port 0092h). These two a20 gate sources are
logically ORed such that both sources must be deasserted to cause the CPU’s a20 output
to be gated Low.
The SCP a20 gate command is detected when the CPU issues the standard command
write of D1h to the SCP Command Port (SCPCMD) register (Port 0064h), followed by a
data write to the SCP Data Port (SCPDATA) register (Port 0060h). Bit 1 of the write to the
SCP Data Port (SCPDATA) register drives the a20 control logic. A value of 1 allows the
CPU’s a20 signal to propagate to the core logic, while a value of 0 allows the CPU’s a20
signal to be driven Low, as long as no other a20 gate control sources are forcing the CPU’s
a20 signal to propagate.
In addition to the SCP a20 gate command emulation, the A20G_CTL bit in the System
Control Port A (SYSCTLA) register (Port 0092h) can also be used for alternate a20 signal
control. Setting the A20G_CTL bit allows the CPU’s a20 signal to be propagated to the
system logic. Clearing this bit (default state) allows the a20 signal to be driven Low as long
as no other a20 gate control sources are forcing the a20 signal to propagate.
6.5.9 Clocking Considerations
As a result of an ÉlanSC520 microcontroller system reset event, the internal PLLs are re-
started. The PLL start-up time from the deassertion of the system reset source is 10 ms.
6.5.10 Software Considerations
The CPU cache, SDRAM controller write buffer, and PCI transaction queues are discarded
as a result of a system reset.