AMD Elan SC520, User Manual, Page: 122 / 444

Am5
x
86
®
CPU
7-4 Élan™SC520 Microcontroller User’s Manual
7.4.2 Cache Memory Management
The ÉlanSC520 microcontroller contains a 16-Kbyte unified code and data cache. Cache
operation defaults to write-back cache mode. However, this mode can be disabled by setting
the Cache Write Mode (CACHE_WR_MODE) bit in the Am5
x
86 CPU Control register
(MMCR offset 02h). Note that the cache should be flushed when switching this bit from
write-back to write-through cache mode.
The cache that is internal to the CPU is historically referred to as the level 1 (L1) cache.
Cache that is located external to the CPU is called level 2 (L2). The ÉlanSC520
microcontroller does not have the control mechanism or the pins to support an L2 cache.
The L1 cache can be configured through the standard cache configuration bits in the CPU’s
machine status (CR0) register. The Cache Disable (CD) and Not Write-Through (NW) bits
are decoded as shown in Table 7-3.
If paging is enabled in the CPU, then cacheability as well as cache write policy can be
controlled on a per-page basis via control bits in the page tables. Note that the
CACHE_WR_MODE bit in the Am5
x
86 CPU Control (CPUCTL) register must be set to
write-back cache mode for write-back behavior to occur.
Caching is controlled by the memory management subsystem on a per-access basis. For
example, GP bus and PCI bus accesses are not cached. The programmer has control over
which regions of memory (SDRAM and ROM) are cacheable and which are not. This is
described in detail in Chapter 4, “System Address Mapping”.
7.4.3 Clocking Considerations
The Am5
x
86 CPU bus frequency in the ÉlanSC520 microcontroller is always 33 MHz.
However, the Am5
x
86 CPU core frequency is programmable to be 100 MHz or 133 MHz.
The clock speed of the Am5
x
86 CPU core defaults to 100 MHz, but can be changed
dynamically via the Am5
x
86 CPU Control (CPUCTL) register (MMCR offset 02h). Systems
that maintain relatively high cache hit rates benefit more from the higher core speeds,
because they are not dependent on external bus activity for accessing ROM or SDRAM.
The clock speed change is transparent to the system, with the exception that there is
approximately 1-ms delay to allow the Am5
x
86 CPU’s clock PLLs to stabilize. Following
the clock speed configuration, the ÉlanSC520 microcontroller’s clock control logic
automatically forces the Am5
x
86 CPU’s cache to be flushed, and waits for the completion
of the flush before changing the PLLs’ frequency select (caching is also disabled for any
subsequent memory read cycles during the flush operation). Since the CPU PLLs require
approximately 1 ms to stabilize following the speed change, all Am5
x
86 CPU cache
snooping is suspended. However, since the cache was previously flushed, there are no
Table 7-3 Cache Configuration Options
CD NW Operating Mode
1 1 Cache line fills, cache write-throughs, and cache invalidations are disabled. To
completely disable the cache, set both CD and NW to 1 and flush the cache by
executing a WBINVD or INVD instruction.
1 0 Cache line fills are disabled. Cache write-throughs and cache invalidations are
enabled. This configuration allows software to disable the cache for a short time,
then re-enable it without flushing the original contents.
0 1 Invalid setting. A general-protection exception with an error code of 0 is generated.
0 0 Cache line fills, cache write-throughs, and cache invalidations are enabled. This
is the normal operating configuration.