AMD Elan SC520, User Manual, Page: 83 / 444

System Address Mapping
Élan™SC520 Microcontroller User’s Manual 4-5
“Programmable Input/Output”, which describes enabling the actual programmable I/O (PIO)
pins that can be shared with other functions.
4.3.2 Programmable Address Region (PAR) Registers
Programmable Address Region (PAR) registers provide a common programming interface
to configure memory space and I/O space regions in an ÉlanSC520 microcontroller system.
As referenced in Table 4-4, the PAR registers are primarily used to define the address
regions of ROM and GP bus, as well as to set attributes for ROM and SDRAM regions.
The first two PAR registers (PAR 0 and PAR 1) also allow the user to redirect CPU accesses
that normally fall into SDRAM space to the PCI bus, for special cases that require this
functionality. The ÉlanSC520 microcontroller provides a total of 16 PAR registers to provide
the user with flexibility in organizing memory space and I/O space in the system. They are
organized in a priority scheme starting with the lowest register (PAR 0). Thus, if overlapping
regions are programmed, the lowest number PAR register takes priority. The PAR registers
are 32 bits each and reside in the MMCR space.
Since the ÉlanSC520 microcontroller supports PC/AT-compatible peripherals, the regions
required for these peripherals are fixed in I/O space and are not relocatable via PAR
registers. This includes the GP bus DMA controller, the programmable interval timer (PIT),
the programmable interrupt controller (PIC), the two 16550-compatible UARTs, the real-
time clock (RTC), and the PC/AT port logic.
Figure 4-1 illustrates the layout of the 32-bit PAR register. Note that the registers are
organized in four sections, as follows:
■ The Target (TARGET) bit field defines the destination of the cycle (i.e., ROM, GP bus,
etc.).
■ The Attribute (ATTR) bit field allows memory regions to be programmed with special
conditions such as write-protection and noncacheability for ROM or SDRAM access or
selects a specific chip select for GP bus accesses.
■
The Page Size (PG_SZ) bit defines the size of each memory page within the regions.
■ The Region Size/Start Address (SZ_ST_ADR) bit field is used to define both the
beginning of the region and the total size of the region (in conjunction with the Page
Size
bit).
Note that the PAR register is used to define only the actual address space for the targets;
it does not control the parameters for timing and bus width required for ROM and GP bus
devices. Those controls must be programmed independently in the ROM controller and GP
bus controller configuration registers.