Agilent Technologies Agilent 4396B, Service Manual

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Single-Loop Operation at Frequency Spans > 45 MHz. In the single-loop mode , the V CO
signal loops back to the phase detector through the 1/4 divider and the 1/16 divider . The V CO
frequency ( F
vco
) is divided by 64 and then compared with the FRA C N OSC signal frequency
(F
frac
) (31.25 MHz to 62.5 MHz) in the phase detector . Phase locking imposes the condition
of F
frac
= F
vco
/64. Therefore , the output frequency (F
vco
) is locked to F
frac
x 64. The F
vco
sweeps from 2 GHz (31.25 MHz x 64) to 4 GHz (62.5 MHz x 64) according to the FRA C N
OSC; swept signal. The frequency range actually used in the analyzer is 2.05858 GHz (at a
measurement frequency 0 Hz) to 3.85858 GHz (at a measurement frequency 1.82 GHz).
Triple-Loop Operation at Frequency Spans 45 MHz. In the triple-loop mode , the V CO
signal loops back to the phase detector through the 1/4 divider and the mixer . The V CO
frequency (F
vco
) is mixed with the STEP OSC output (F
step
) in the mixer . The mixer then
produces the shifted frequency of F
vco
/4 - F
step
. The mixer output is compared with the FRA C
N OSC output signal in the phase detector . Phase locking imposes the condition of F
frac
=
F
vco
/4 - F
step
. Therefore , the output frequency F
vco
is locked to F
frac
x 4 + F
step
x 4. The F
vco
sweeps over the appropriate range determined by the start and stop setting according to the
F
frac
.
The F
step
is determined by the center frequency of the analyzer as shown in T able 11-1 . The
F
frac
sweeps between f (start frequency + 2.05858 GHz)/4 - F
step
g /4 to f (stop frequency +
2.05858 GHz)/4 - F
step
g /4.
Digital Control Signals for the A4A2 Receiver RF
The A4A2 1st LO has the decoder circuitry for the following digital control signals . These
signals come from the A1 CPU . The decoded signals are supplied to the A4A2 Receiver RF
through the cable at A4A1J2.
NA/SA Switch Control Signal
AZ (A uto Zero) Control Signal
A3A1 ALC
The A3A1 ALC generates the level-controlled 21.42 MHz IF signal, an 8 MHz reference signal,
and a 40 kHz reference signals .
The 21.42 MHz signal is supplied to the A3A2 2nd LO and converted to a 2.05858 GHz IF
signal through the source rst converter . The 8 MHz and 40 kHz signals are supplied to the A6
receiver IF and used as reference signals .
The A3A1 ALC consists of the following circuits:
Divider
Source OSC (Source Oscillator)
ALC (A utomatic Leveling Control)
Divider
The divider contains a 1/5 divider and a 1/200 divider . The 40 MHz reference frequency from
the A5 synthesizer is down converted to 8 MHz and 40 kHz through the two dividers . The two
signals are then supplied to the A6 receiver IF through the A20 motherboard.
Source OSC
The source OSC (source oscillator) is a phase locked oscillator . The output signal is phase locked
to the 40 kHz frequency of the divider output. The oscillator generates the 85.68 MHz signal.
The signal divided by the 1/4 divider . The resulting 21.42 MHz signal is supplied to the ALC
circuit.
Theory of Operation 11-19