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The
comb
generator
receives
the
40
MHz
reference
signal
from
the
REF
OSC
and
multiples
the
fundamental
signal
into
a
comb
of
harmonic
frequencies
(40
MHz
x
N).
The
level
of
the
harmonics
is
adjusted
in
the
Comb
Generator
A
djustment.
The
phase
locked
oscillator
consists
of
a
470
MHz
to
930
MHz
V
CO
,
a
phase
detector
,
a
mixer
,
a
pretune
D
A
C
and
61
converters
.
See
Figure
11-6.
The
V
CO
frequency
(F
vco
)
is
mixed
with
the
comb
generator
output
in
the
mixer
.
The
mixer
produces
multiple
harmonics
(F
vco
6
40
MHz
x
N)
through
the
LPF
(low
pass
lter).
The
mixer
output
is
compared
with
the
10
MHz
reference
signal
in
the
phase
detector
.
Phase
locking
imposes
the
condition
of
10
MHz
=
F
vco
6
40
MHz
x
N,
and
the
loop
locks
to
the
nearest
40
MHz
harmonic
satisfying
that
condition.
The
initial
frequency
(F
vco
)
is
set
to
the
desired
harmonic
frequency
of
40
MHz
x
N
(N
=
12
to
23)
using
the
pretune
D
A
C.
This
locks
the
output
frequency
(F
vco
)
to
the
desired
40
MHz
x
N
6
10
MHz
selection
of
the
frequencies
listed
in
T
able
11-1 .
The
polarity
of
the
10
MHz
oset
is
controlled
by
the
61
converters
in
the
loop
.
An
unlock
detector
monitors
the
control
voltage
to
the
V
CO
.
When
the
control
voltage
is
out
of
limits
,
the
detector
sends
the
status
to
the
A1
CPU
.
The
A1
CPU
causes
the
message
CA
UTION:
PHASE
LOCK
LOOP
UNLOCKED
to
be
displayed.
The
pretune
D
A
C
values
are
predened
by
performing
the
Step
Pretune
Correction
Constants
and
are
stored
in
the
EEPROM
in
the
A1
CPU
.
Multiplier
(X
13)
The
multiplier
receives
the
40
MHz
reference
signal
and
generates
a
520
MHz
signal.
This
signal
is
supplied
to
A3A2
2nd
LO
and
is
used
to
generate
the
second
local
oscillator
signal.
See
Figure
11-6.
The
520
MHz
signal
level
is
adjusted
in
the
520
MHz
Level
A
djustment.
A4A1
1st
LO
The
A4A1
1st
LO
generates
the
swept
1st
local
oscillator
signal
2.05858
GHz
to
3.85858
GHz
with
1
mHz
resolution.
The
sweep
range
depends
on
the
start
and
stop
(or
center
and
span)
settings
of
the
analyzer
.
The
signal
frequency
sweeps
between
the
start
frequency
+
2.05858
GHz
to
the
stop
frequency
+
3.85858
GHz.
The
1st
local
oscillator
signal
is
supplied
to
the
A3A3
source
and
the
A4A2
receiver
RF
.
In
A3A3,
the
local
oscillator
signal
is
used
to
convert
the
2.05858
GHz
IF
(intermediate
frequency)
signal
to
the
100
kHz
to
1.8
GHz
RF
signal.
A4A2
also
uses
the
rst
local
to
convert
the
RF
input
signal
to
the
IF
signal.
In
addition,
the
A4A1
1st
LO
decodes
two
digital
control
signals
for
the
A4A2
Receiver
RF
,
and
the
decoded
signals
are
supplied
to
A4A2.
1st
Local
OSC
Circuit
The
1st
local
oscillator
circuit
is
a
phase
locked
oscillator
.
The
output
signal
is
phase
locked
to
the
FRA
C
N
OSC
output
signal.
The
oscillator
contains
a
2.05858
GHz
to
3.85858
GHz
V
CO
,
a
phase
detector
,
a
1/4
divider
,
a
mixer
,
a
1/16
divider
,
and
a
single/triple
switch.
See
Figure
11-8.
The
single/triple
switch
is
for
the
single/triple
mode
and
switches
the
V
CO
signal
to
one
of
the
mixers
and
the
1/16
divider
.
An
unlock
detector
monitors
the
control
voltage
to
the
V
CO
.
When
the
control
voltage
is
out
of
the
limits
,
the
detector
sends
the
status
to
the
A1
CPU
.
The
A1
CPU
causes
the
message
CA
UTION:
PHASE
LOCK
LOOP
UNLOCKED
to
be
displayed.
11-18
Theory
of
Operation
Summary of Contents for Agilent 4396B
Page 10: ......
Page 32: ......
Page 43: ...Figure 2 7 CAL OUT Level Adjustment Location Adjustments and Correction Constants 2 11 ...
Page 46: ...Figure 2 10 Comb Generator Output 2 14 Adjustments and Correction Constants ...
Page 62: ...Figure 2 26 Final Gain Adjustment Location 2 30 Adjustments and Correction Constants ...
Page 76: ...Figure 3 1 Troubleshooting Organization 3 2 T roubleshooting ...
Page 84: ......
Page 90: ...Figure 5 1 Power Supply Lines Simpli ed Block Diagram 5 2 Power Supply T roubleshooting ...
Page 107: ...Figure 5 12 Power Supply Block Diagram 1 Power Supply T roubleshooting 5 19 ...
Page 108: ...Figure 5 13 Power Supply Block Diagram 2 5 20 Power Supply T roubleshooting ...
Page 109: ...Figure 5 14 Power Supply Block Diagram 3 Power Supply T roubleshooting 5 21 ...
Page 110: ......
Page 112: ...Figure 6 1 Digital Control Group Simpli ed Block Diagram 6 2 Digital Control T roubleshooting ...
Page 124: ......
Page 126: ...Figure 7 1 Source Group Block Diagram 7 2 Source Group T roubleshooting ...
Page 160: ...Figure 8 1 Receiver Group Simpli ed Block Diagram 8 2 Receiver Group T roubleshooting ...
Page 168: ......
Page 184: ...Figure 10 6 External Test Setup 1 Figure 10 7 External Test Setup 2 10 10 Service Key Menus ...
Page 185: ...Figure 10 8 External Test Setup 3 Figure 10 9 External Test Setup 4 Service Key Menus 10 11 ...
Page 226: ...Figure 11 3 Power Supply Functional Group Simpli ed Block Diagram 11 6 Theory of Operation ...
Page 231: ...Figure 11 5 Digital Control Group Simpli ed Block Diagram Theory of Operation 11 11 ...
Page 235: ...Figure 11 6 Source Simpli ed Block Diagram Theory of Operation 11 15 ...
Page 244: ...Figure 11 7 Receiver Simpli ed Block Diagram 11 24 Theory of Operation ...
Page 249: ...Figure IDC5S11001 here Figure 11 8 4396B Source Group Block Diagram Theory of Operation 11 29 ...
Page 254: ...Figure 12 1 Top View Major Assemblies 12 4 Replaceable Parts ...
Page 290: ...Figure 12 36 Main Frame Assembly Parts 17 19 12 40 Replaceable Parts ...
Page 294: ......
Page 308: ......
Page 311: ...Figure C 1 Power Cable Supplied Power Requirement C 3 ...
Page 312: ......
Page 324: ......