R3267 Series Spectrum Analyzer Operation Manual (Vol.1)
5.2.8 Status Bytes
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5.2.8
Status Bytes
The analyzer has a hierarchical status register structure which complies with IEEE Standard 488.2-1987.
This is used to send information on the status of various aspects of a device to the controller. This section
explains the status byte and event assignments operation models.
(1)
Status Register
The analyzer uses the status register model defined by IEEE Standard 488.2-1987. This consists of
a condition register, an event register and an enable register.
(a) Condition Register
The condition register continuously monitors the status of devices, showing their latest status.
However, this register is used internally, so no data can be written into or read out from this
register.
(b) Event Register
The event register latches and retains the status information from the condition register (in some
cases, it retains status changes).
Once the register is set, the condition is maintained until a query command reads out the
information or the register is reset by means of the *CLS command.
No data can be written into the event register.
(c) Enable Register
The enable register specifies which bit in the event register is to be used as the valid status to
generate a summary. The enable register is ANDed with the event register. The OR of the result
of the AND operation is generated as a summary. The summary is written into the following
status byte registers.
Any data can be written into the enable register.
0
1
n-1
n
0
1
n-1
n
0
1
n-1
n
&
&
&
&
OR
Condition
register
Event
register
Enable
register
