NXP Semiconductors LPC1751, Руководство пользователя, Страница: 724 / 808

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
FT DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
FT DRAFT DRAFT DRAFT DRA
UM10360_0 © NXP B.V. 2009. All rights reserved.
User manual Rev. 00.06 — 5 June 2009 724 of 808
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 User Guide
3.4.2 Fault escalation and hard faults
All faults exceptions except for hard fault have configurable exception priority, see Section
37–1.3.9 “System Handler Priority Registers” . Software can disable execution of the
handlers for these faults, see Section 37–1.3.10 “System Handler Control and State
Register” .
Usually, the exception priority, together with the values of the exception mask registers,
determines whether the processor enters the fault handler, and whether a fault handler
can preempt another fault handler. as described in
Section 34–3.3 .
In some situations, a fault with configurable priority is treated as a hard fault. This is called
priority escalation , and the fault is described as escalated to hard fault . Escalation to
hard fault occurs when:
•
A fault handler causes the same kind of fault as the one it is servicing. This escalation
to hard fault occurs because a fault handler cannot preempt itself because it must
have the same priority as the current priority level.
•
A fault handler causes a fault with the same or lower priority as the fault it is servicing.
This is because the handler for the new fault cannot preempt the currently executing
fault handler.
•
An exception handler causes a fault for which the priority is the same as or lower than
the currently executing exception.
•
A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault
does not escalate to a hard fault. This means that if a corrupted stack causes a fault, the
fault handler executes even though the stack push for the handler failed. The fault handler
operates but the stack contents are corrupted.
Remark: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can
preempt any exception other than Reset, NMI, or another hard fault.
3.4.3 Fault status registers and fault address registers
The fault status registers indicate the cause of a fault. For bus faults and memory
management faults, the fault address register indicates the address accessed by the
operation that caused the fault, as shown in
Table 34–614 .
Table 614. Fault status and fault address registers
Handler Status register
name Address register
name Register description
Hard fault HFSR - Section 37–1.3.12 “Hard Fault Status Register”
Memory
management
fault MMFSR MMFAR Section 37–1.3.13 “Memory Management Fault Address Register”
Section 37–1.3.11.1 “Memory Management Fault Status Register”
Bus fault BFSR BFAR Section 37–1.3.11.2 “Bus Fault Status Register”
Section 37–1.3.14 “Bus Fault Address Register”
Usage fault UFSR - Section 37–1.3.11.3 “Usage Fault Status Register”