
DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
FT DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
FT DRAFT DRAFT DRAFT DRA
UM10360_0
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 00.06 — 5 June 2009
704 of 808
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 User Guide
3.1.4 Exceptions and interrupts
The Cortex-M3 processor supports interrupts and system exceptions. The processor and
the
Nested Vectored Interrupt Controller
(NVIC) prioritize and handle all exceptions. An
exception changes the normal flow of software control. The processor uses handler mode
to handle all exceptions except for reset. See
and
for more information.
The NVIC registers control interrupt handling. See
Section 37–1.2 “Nested Vectored
for more information.
3.1.5 Data types
The processor:
•
supports the following data types:
–
32-bit words
–
16-bit halfwords
–
8-bit bytes
•
supports 64-bit data transfer instructions.
•
manages all data memory accesses as little-endian. See
for more
information.
3.1.6 The Cortex Microcontroller Software Interface Standard
For a Cortex-M3 microcontroller system, the
Cortex Microcontroller Software Interface
Standard
(CMSIS) defines:
•
a common way to:
–
access peripheral registers
–
define exception vectors
•
the names of:
–
the registers of the core peripherals
–
the core exception vectors
•
a device-independent interface for RTOS kernels, including a debug channel.
The CMSIS includes address definitions and data structures for the core peripherals in the
Cortex-M3 processor. It also includes optional interfaces for middleware components
comprising a TCP/IP stack and a Flash file system.
CMSIS simplifies software development by enabling the reuse of template code and the
combination of CMSIS-compliant software components from various middleware vendors.
Software vendors can expand the CMSIS to include their peripheral definitions and
access functions for those peripherals.
This document includes the register names defined by the CMSIS, and gives short
descriptions of the CMSIS functions that address the processor core and the core
peripherals.
Remark:
This document uses the register short names defined by the CMSIS. In a few
cases these differ from the architectural short names that might be used in other
documents.