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UM10360_0
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 00.06 — 5 June 2009
614 of 808
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 User Guide
To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements
tightly-coupled system components that reduce processor area while significantly
improving interrupt handling and system debug capabilities. The Cortex-M3 processor
implements a version of the Thumb instruction set, ensuring high code density and
reduced program memory requirements. The Cortex-M3 instruction set provides the
exceptional performance expected of a modern 32-bit architecture, with the high code
density of 8-bit and 16-bit microcontrollers.
The Cortex-M3 processor closely integrates a configurable
nested interrupt controlle
r
(NVIC), to deliver industry-leading interrupt performance. The NVIC includes a
non-maskable interrupt
(NMI), and provides up to 256 interrupt priority levels. The tight
integration of the processor core and NVIC provides fast execution of
interrupt service
routines
(ISRs), dramatically reducing the interrupt latency. This is achieved through the
hardware stacking of registers, and the ability to suspend load-multiple and store-multiple
operations. Interrupt handlers do not require any assembler stubs, removing any code
overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead
when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a
deep sleep function that enables the entire device to be rapidly powered down.
LPC17xx devices support additional reduced power modes, see
for details.
1.1.1 System level interface
The Cortex-M3 processor provides multiple interfaces using AMBA technology to provide
high speed, low latency memory accesses. It supports unaligned data accesses and
implements atomic bit manipulation that enables faster peripheral controls, system
spinlocks and thread-safe Boolean data handling.
The Cortex-M3 processor has an optional
memory protection unit
(MPU) that provides
fine grain memory control, enabling applications to implement security privilege levels,
separating code, data and stack on a task-by-task basis. Such requirements are
becoming critical in many embedded applications such as automotive. The MPU is
included in LPC17xx devices.
1.1.2 Integrated configurable debug
The Cortex-M3 processor implements a complete hardware debug solution. This provides
high system visibility of the processor and memory through either a traditional JTAG port
or a 2-pin
Serial Wire Debug
(SWD) port that is ideal for microcontrollers and other small
package devices. The MCU vendor determines the debug feature configuration and
therefore this can differ across different devices and families.
For system trace the processor integrates an
Instrumentation Trace Macrocell
(ITM)
alongside data watchpoints and a profiling unit. To enable simple and cost-effective
profiling of the system events these generate, a
Serial Wire Viewer
(SWV) can export a
stream of software-generated messages, data trace, and profiling information through a
single pin.
The optional
Embedded Trace Macrocell
(ETM) delivers unrivalled instruction trace
capture in an area far smaller than traditional trace units, enabling many low cost MCUs to
implement full instruction trace for the first time.