![background image](http://html1.mh-extra.com/html/nec/v850e-dx3/v850e-dx3_preliminary-users-manual_4115960532.webp)
532
Chapter 16
Asynchronous Serial Interface (UARTA)
Preliminary User’s Manual U17566EE1V2UM00
16.5.10
Receive data noise filter
This filter samples the RXDAn pin using the base clock of the prescaler output.
When the same sampling value is read twice, the match detector output
changes and the RXDAn signal is sampled as the input data. Therefore, data
not exceeding 2 clock width is judged to be noise and is not delivered to the
internal circuit (see
Figure 16-10
). See
“Base clock“ on page 533
regarding the
base clock.
Moreover, since the circuit is as shown in
Figure 16-9
, the processing that
goes on within the receive operation is delayed by 3 clocks in relation to the
external signal status.
Figure 16-9
Noise filter circuit
Figure 16-10
Timing of RXDAn signal judged as noise
M
a
tch
detector
In
B
as
e clock (f
UCLK
)
RXDAn
Q
In
LD_EN
Q
Intern
a
l
s
ign
a
l C
Intern
a
l
s
ign
a
l B
In
Q
Intern
a
l
s
ign
a
l A
Intern
a
l
s
ign
a
l B
B
as
e clock
RXDAn (inp
u
t)
Intern
a
l
s
ign
a
l C
Mi
s
m
a
tch
(j
u
dged
as
noi
s
e)
Intern
a
l
s
ign
a
l A
Mi
s
m
a
tch
(j
u
dged
as
noi
s
e)
M
a
tch
M
a
tch
electronic components distributor