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463
16-bit Multi-Purpose Timer G (TMG)
Chapter 13
Preliminary User’s Manual U17566EE1V2UM00
(b) Example: Capture where both edges of TIGnm are valid (match and
clear)
For the timing chart TMGn0 is selected as the counter corresponding to
TOGn1, and 0FFFH is set in GCCn0.
Figure 13-12
Timing when both edges of TIGnm are valid (match and clear)
Note
The figure above shows an image. In actual circuitry, 3 to 4 periods of the
count-up signal (f
COUNT
) are required from the input of a waveform to TOGn1
until a capture interrupt is output. (See
Figure 13-4 on page 454
.)
Caution
If two or more match and clear events occur between captures, a software-
based measure needs to be taken to count INTCCGn0 or INTCCGn5.
(c) When 0000H is set in GCCn0 or GCCn5 (match and clear)
When 0000H is set in GCCn0 (GCCn5), the value of the counter is fixed at
0000H, and does not operate. Moreover, INTCCGn0 (INTCCGn5) continues to
be active.
(d) When FFFFH is set in GCCn0 or GCCn5 (match and clear)
When FFFFH is set in GCCn0 (GCCn5), operation equivalent to the free-run
mode is performed. When an overflow occurs, INTTMGn0 (INTTMGn1) is
generated, but INTCCGn0 (INTCCGn5) is not generated.
0000H
0001H
D0
D1
TMGn0
D0
GCCn1
C ount start
t
0FF F H 0000H
D2
D3
TIGn1
D1
D2
D3
Cl ear
INTTGnCC1
INTTGnCC0
No "match and cl ea r"
No "match and cl ea r"
"Match and c lea r"
CCFG1
f
COUNTx
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