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Chapter 11
16-bit Timer/Event Counter P (TMP)
Preliminary User’s Manual U17566EE1V2UM00
(2)
Operation flow in PWM output mode
Figure 11-23
Software processing flow in PWM output mode (1/2)
FFFFH
16-
b
it co
u
nter
0000H
TPnCE
b
it
TPnCCR0 regi
s
ter
CCR0
bu
ffer regi
s
ter
INTTPnCC0
s
ign
a
l
TOPn0 pin o
u
tp
u
t
TPnCCR1 regi
s
ter
CCR1
bu
ffer regi
s
ter
INTTPnCC1
s
ign
a
l
TOPn1 pin o
u
tp
u
t
D
10
D
00
D
00
D
01
D
00
D
00
D
10
D
10
D
11
D
10
D
10
D
10
D
11
D
10
D
01
D
00
D
10
D
10
D
00
D
10
D
00
D
11
D
11
D
01
D
01
D
01
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