EMR-4000
IM02602009E
Name
Description
Logic.LE8.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE8.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE8.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE8.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE9.Gate Out
Signal: Output of the logic gate
Logic.LE9.Timer Out
Signal: Timer Output
Logic.LE9.Out
Signal: Latched Output (Q)
Logic.LE9.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE9.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE9.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE9.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE9.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE9.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE10.Gate Out
Signal: Output of the logic gate
Logic.LE10.Timer Out
Signal: Timer Output
Logic.LE10.Out
Signal: Latched Output (Q)
Logic.LE10.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE10.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE10.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE10.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE10.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE10.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE11.Gate Out
Signal: Output of the logic gate
Logic.LE11.Timer Out
Signal: Timer Output
Logic.LE11.Out
Signal: Latched Output (Q)
Logic.LE11.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE11.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE11.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE11.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE11.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE11.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE12.Gate Out
Signal: Output of the logic gate
Logic.LE12.Timer Out
Signal: Timer Output
Logic.LE12.Out
Signal: Latched Output (Q)
Logic.LE12.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE12.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE12.Gate In2-I
State of the module input: Assignment of the Input Signal
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Содержание EMR-4000
Страница 61: ...EMR 4000 IM02602009E Ethernet RJ45 Terminal Marking www eaton com 61 1 8 TxD TxD RxD N C N C RxD N C N C...
Страница 423: ...EMR 4000 IM02602009E Name Description Logic LE23 Out inverted Signal Negated Latched Output Q NOT www eaton com 423...
Страница 493: ...EMR 4000 IM02602009E Motor Protection Curves Motor Protection Curve Example 1 www eaton com 493...
Страница 494: ...EMR 4000 IM02602009E Motor Protection Curve Example 2 without RTDs www eaton com 494...
Страница 495: ...EMR 4000 IM02602009E Motor Protection Curve Example 3 with RTDs www eaton com 495...