6-26
Close and Reclose Logic
Date Code 20011205
SEL-311B Instruction Manual
Additional Settings Example 3
Refer to Figure 6.4 and accompanying setting example, showing an application for setting
79STL.
Other Settings Considerations
If no special skip shot or stall open interval timing conditions are desired, make the following
settings:
79SKP =
0
(numeral
0)
79STL =
0
(numeral
0)
Block Reset Timing Setting (79BRS)
The block reset timing setting 79BRS keeps the reset timer from timing. Depending on the
reclosing relay state, the reset timer can be loaded with either reset time:
79RSD (Reset Time from Reclose Cycle)
or
79RSLD (Reset Time from Lockout)
Depending on how setting 79BRS is set, none, one, or both of these reset times can be controlled.
If the reset timer is timing and then 79BRS asserts to:
79BRS = logical
1
reset timing is stopped and does not begin timing again until 79BRS deasserts to:
79BRS = logical
0
When reset timing starts again, the reset timer is fully loaded. Thus, successful reset timing has
to be continuous. Use the RSTMN Relay Word bit to monitor reset timing (see
Monitoring
Open Interval and Reset Timing
earlier in this subsection).
Settings Example 1
The block reset timing setting is:
79BRS = (51P + 51G) * 79CY
Relay Word bit 79CY corresponds to the Reclose Cycle State. The reclosing relay is in one of
the three reclosing relay states at any one time (see Figure 6.5).
When the relay is in the Reset or Lockout States, Relay Word bit 79CY is deasserted to logical 0.
Thus, the 79BRS setting has no effect when the relay is in the Reset or Lockout States. When a
circuit breaker is closed from lockout, there could be cold load inrush current that momentarily
picks up a time-overcurrent element (e.g., phase time-overcurrent element 51PT pickup [51P]
asserts momentarily). But, this assertion of pickup 51P has no effect on reset timing because the
relay is in the Lockout State (79CY = logical 0). The relay will time immediately on reset time
79RSLD and take the relay from the Lockout State to the Reset State with no additional delay
because 79BRS is deasserted to logical 0.
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