CHAPTER 14 SERIAL ARRAY UNIT
Page 373 of 920
(1) Register setting
Figure 14 - 40 Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSIp)
(a)
Serial mode register mn (SMRmn)
(b)
Serial communication operation setting register mn (SCRmn)
(c)
Serial data register mn (SDRmn) (lower 8 bits: SIOp)
(d)
Serial output register m (SOm)... Sets only the bits of the target channel.
(e)
Serial output enable register m (SOEm)... Sets only the bits of the target channel to 1.
(f)
Serial channel start register m (SSm)... Sets only the bits of the target channel to 1.
Remark
: Setting is fixed in the CSI master transmission/reception mode,
: Setting disabled (set to the initial value)
0/1: Set to 0 or 1 depending on the usage of the user
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SMRmn
CKSmn
0/1
CCSmn
0
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
0
MDmn1
0
MDmn0
0/1
Operation clock (f
MCK
) of channel n
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
Interrupt source of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCRmn
TXEmn
1
RXEmn
1
DAPmn
0/1
CKPmn
0/1
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0/1
0
SLCmn1
0
SLCmn0
0
0
1
1
DLSmn0
0/1
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first
Setting of data length
0: 7-bit data length
1: 18-bit data length
Selection of the data and clock phase (For
details about the setting, see
Registers Controlling Serial Array Unit
.)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SDRmn
Baud rate setting
(Operation clock (f
MCK
) division setting)
0
Transmit data setting/receive data register
SIOp
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOm
0
0
0
0
CKOm3
0/1
CKOm2
0/1
CKOm1
0/1
CKOm0
0/1
0
0
0
0
SOm3
0/1
SOm2
0/1
SOm1
0/1
SOm0
0/1
Communication starts when these bits are 1 if the clock phase is
non-reversed (the CKPmn bit of the SCRmn = 0). If the clock phase is
reversed (CKPmn = 1), communication starts when these bits are 0.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
SOEm3
0/1
SOEm2
0/1
SOEm1
0/1
SOEm0
0/1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
0/1
SSm2
0/1
SSm1
0/1
SSm0
0/1
Summary of Contents for RL78/G1H
Page 941: ...R01UH0575EJ0120 RL78 G1H...
