Renesas RL78/G1H, User Manual

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RL78/G1H CHAPTER 12 WATCHDOG TIMER
R01UH0575EJ0120 Rev. 1.20 Page 274 of 920
Dec 22, 2016
12.2 Configuration of Watchdog Timer
The watchdog timer includes the following hardware.
How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the
option byte.
Remark For the option byte, see CHAPTER 26 OPTION BYTE .
Figure 12 - 1 Block Diagram of Watchdog Timer
Remark f
IL
: Low-speed on-chip oscillator clock
Table 12 - 1 Configuration of Watchdog Timer
Item Configuration
Counter Internal counter (17 bits)
Control register Watchdog timer enable register (WDTE)
Table 12 - 2 Setting of Option Bytes and Watchdog Timer
Setting of Watchdog Timer Option Byte (000C0H)
Watchdog timer interval interrupt Bit 7 (WDTINT)
Window open period Bits 6 and 5 (WINDOW1, WINDOW0)
Controlling counter operation of watchdog timer Bit 4 (WDTON)
Overflow time of watchdog timer Bits 3 to 1 (WDCS2 to WDCS0)
Controlling counter operation of watchdog timer (in HALT/STOP mode) Bit 0 (WDSTBYON)
Clock
input
controller
Reset
output
controller
Internal reset signal
Selector
Internal
counter
(17 bits)
Window size check
Write detector to
WDTE except ACH
Interval time interrupt
Interval time controller
(Count value overflow time × 3/4) + 1/2 f
IL
)
WDTINT of option byte
(000C0H)
WDCS2 to WDCS0 of
option byte (000C0H)
f
IL
/2
6
to f
IL
/2
16
f
IL
Overflow signal
Window size
decision signal
Count clear
signal
Internal bus
WINDOW1 and WINDOW0 of
option byte (000C0H)
WDTON of option byte
(000C0H)
Watchdog timer enable
register (WDTE)