Renesas RL78/G1H, User Manual

Page: 311 / 941

RL78/G1H CHAPTER 13 A/D CONVERTER
R01UH0575EJ0120 Rev. 1.20 Page 293 of 920
Dec 22, 2016
Note 1. For the second and subsequent conversion in sequential conversion mode, the conversion start time and stabilization
wait time for A/D power supply do not occur after a hardware trigger is detected (see
Table 13 - 4 ).
Note 2. 1.8 V
≤
V
DD
≤
3.6 V
Note 3. 2.4 V
≤
V
DD
≤
3.6 V
Note 4. 2.7 V ≤ V
DD
≤ 3.6 V
Note 5. These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is selected,
the values are shorter by two cycles of the conversion clock (f
AD
).
Caution 1. The A/D conversion time must also be within the relevant range of conversion times (t
CONV
) described in 31.6.1
A/D converter characteristics.
Note that the conversion time (t
CONV
) does not include the A/D power supply stabilization wait time.
Caution 2. Rewrite the FR2 to FR0, LV1 and LV0 bits to other than the same data while conversion is stopped (ADCS = 0,
ADCE = 0).
Caution 3. The above conversion time does not include conversion state time. Conversion state time add in the first
conversion. Select conversion time, taking clock frequency errors into consideration.
Caution 4. When hardware trigger wait mode, specify the conversion time, including the A/D power supply stabilization wait
time from the hardware trigger detection.
Remark f
CLK
:
CPU/peripheral hardware clock frequency
Table 13 - 6 A/D Conversion Time Selection (4/4)
(4) When there is A/D power supply stabilization wait time Low-voltage mode 1, 2
(hardware trigger wait mode
Note 1
)
A/D Converter Mode
Register 0 (ADM0)
Mode Conversion
Clock
(f
AD
)
Number of
A/D Power
Supply
Stabilization
Wait Clock
Number of
Conversion
Clock Note 5
A/D Power
Supply
Stabilization
Wait Time +
Conversion
Time
A/D Power Supply Stabilization Wait Time
+ Conversion Time at 10-Bit Resolution
1.8 V ≤ V
DD
≤ 3.6 V Note 2 Note 3 Note 4
FR
2
FR
1
FR
0
LV
1
LV
0
f
CLK
=
1 MHz
f
CLK
=
4 MHz
f
CLK
=
8 MHz
f
CLK
=
16 MHz
f
CLK
=
32 MHz
0 0 0 1 0 Low-
voltage1
f
CLK
/64 2 f
AD
19 f
AD
(number of
sampling
clock:
7 f
AD
)
1344/f
CLK
Setting
prohibited
Setting
prohibited
Setting
prohibited
84 μ s 42 μ s
0 0 1 f
CLK
/32 672/f
CLK
84 μ s 42 μ s 21 μ s
0 1 0 f
CLK
/16 336/f
CLK
84 μ s 42 μ s 21 μ s 10.5 μ s
0 1 1 f
CLK
/8 168/f
CLK
42 μ s 21 μ s 10.5 μ s 5.25 μ s
1 0 0 f
CLK
/6 126/f
CLK
31.25 μ s 15.75 μ s 7.875 μ s 3.9375 μ s
1 0 1 f
CLK
/5 105/f
CLK
105 μ s 26.25 μ s 13.125 μ s 6.5625 μ s 3.238125
μ s
1 1 0 f
CLK
/4 84/f
CLK
84 μ s 21 μ s 10.5 μ s 5.25 μ s 2.625 μ s
1 1 1 f
CLK
/2 42/f
CLK
42 μ s 10.5 μ s 5.25 μ s 2.625 μ s Setting
prohibited
0 0 0 1 1 Low-
voltage2
f
CLK
/64 2 f
AD
17 f
AD
(number of
sampling
clock:
5 f
AD
)
1216/f
CLK
Setting
prohibited
Setting
prohibited
Setting
prohibited
76 μ s 38 μ s
0 0 1 f
CLK
/32 608/f
CLK
76 μ s 38 μ s 19 μ s
0 1 0 f
CLK
/16 304/f
CLK
76 μ s 38 μ s 19 μ s 9.5 μ s
0 1 1 f
CLK
/8 152/f
CLK
38 μ s 19 μ s 9.5 μ s 4.75 μ s
1 0 0 f
CLK
/6 114/f
CLK
28.5 μ s 14.25 μ s 7.125 μ s 3.5625 μ s
1 0 1 f
CLK
/5 95/f
CLK
96 μ s 23.75 μ s 11.875 μ s 5.938 μ s 2.9688 μ s
1 1 0 f
CLK
/4 76/f
CLK
76 μ s 19 μ s 9.5 μ s 4.75 μ s 2.375 μ s
1 1 1 f
CLK
/2 38/f
CLK
38 μ s 9.5 μ s 4.75 μ s 2.375 μ s Setting
prohibited