CHAPTER 14 SERIAL ARRAY UNIT
Page 366 of 920
(2) Operation procedure
Figure 14 - 33 Initial Setting Procedure for Master Reception
Figure 14 - 34 Procedure for Stopping Master Reception
Release the serial array unit from the reset status
and start clock supply.
Setting the PER0 register
Starting initial setting
Setting the SPSm register
Setting the SMRmn register
Setting the SCRmn register
Setting the SDRmn register
Setting the SOm register
Setting port
Writing to the SSm register
Completing initial setting
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate (setting the transfer clock
by dividing the operation clock (f
MCK
)).
Set the initial output level of the serial clock
(CKOmn).
Enable clock output of the target channel by setting
a port register and a port mode register.
Set the SSmn bit of the target channel to 1
(SEmn bit = 1: to enable operation).
Initial setting is completed.
Set dummy data to the SIOp register (bits 7 to 0 of
the SDRmn register) and start communication.
Write 1 to the STmn bit of the target channel.
(SEmn = 0: to operation stop status)
Writing the STm register
Starting setting to stop
Changing setting of the
SOEm register
Stop setting is completed
Set the SOEmn bit to 0 and stop the output of the
target channel.
After the stop setting is completed, go to the next
processing.
TSFmn = 0?
No
If there is any data being transferred, wait for their
completion.
(If there is an urgent must stop, do not wait.)
Yes
The levels of the serial clock (CKOmn) on the
target channel can be changed if necessitated by
an emergency.
Changing setting of the
SOm register
Setting the PER0 register
Reset the serial array unit by stopping the clock
supply to it.
(Selective)
(Selective)
(Selective)
(Essential)
(Essential)
Summary of Contents for RL78/G1H
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