Renesas RL78/G1H, User Manual

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RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 220 of 920
Dec 22, 2016
Figure 7 - 67 Operation Procedure When PWM Function Is Used (1/2)
(Remark is listed on the next page.)
Software Operation Hardware Status
TAU
default
setting Input clock supply for timer array unit m is stopped
(Clock supply is stopped and writing to each register
is disabled.)
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Input clock supply for timer array unit m is supplied.
Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel
default
setting Sets timer mode registers mn, mp (TMRmn, TMRmp) of
two channels to be used (determines operation mode of
channels).
An interval (period) value is set to timer data register mn
(TDRmn) of the master channel, and a duty factor is set
to the TDRmp register of the slave channel. Channel stops operating.
(Clock is supplied and some power is consumed.)
Sets slave channel.
The TOMmp bit of timer output mode register m
(TOMm) is set to 1 (slave channel output mode).
Sets the TOLmp bit.
Sets the TOmp bit and determines default level of the
TOmp output.
Sets the TOEmp bit to 1 and enables operation of
TOmp.
Clears the port register and port mode register to 0.
The TOmp pin goes into Hi-Z output state.
The TOmp default setting level is output when the port
mode register is in output mode and the port register is
0.
TOmp does not change because channel stops
operating.
The TOmp pin outputs the TOmp set level.