Renesas RL78/G1H, User Manual

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RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS
R01UH0575EJ0120 Rev. 1.20 Page 895 of 920
Dec 22, 2016
Note 1. Excludes quantization error (±1/2 LSB).
Note 2. This value is indicated as a ratio (% FSR) to the full-scale value.
31.6.2 POR characteristics
Note 1. However, when the operating voltage falls while the LVD is off, enter STOP mode, or enable the reset status using the
voltage detection function or external reset pin before the voltage falls below the operating voltage range shown in
31.4
AC Characteristics .
Note 2. Minimum time required for a POR reset when V
DD
exceeds below V
PDR
. This is also the minimum time required for a
POR reset from when V
DD
exceeds below 0.7 V to when V
DD
exceeds V
POR
while STOP mode is entered or the main
system clock (f
MAIN
) is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control
register (CSC).
(2) When reference voltage (+) = V
DD
(ADREFP0 = 0), reference voltage ( ‒ ) = V
SS
(ADREFM = 0),
target pin: ANI0 to ANI2, ANI13, ANI14, ANI19
(T
A
= ‒ 40 to +85 °C, 1.8 V
≤
V
DD
≤
3.6 V, V
SS
= 0 V, Reference voltage (+) = V
DD
, Reference voltage ( ‒ ) = V
SS
)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 10 bit
Overall error
Note 1 AINL 10-bit resolution 1.8 V
≤
V
DD
≤
3.6 V 1.2
±
7.0 LSB
Conversion time t
CONV
10-bit resolution
Target pin: ANI0 to ANI2, ANI13, ANI14, ANI19 2.7 V ≤ V
DD
≤ 3.6 V 3.1875 39 μ s
1.8 V ≤ V
DD
≤ 3.6 V 17 39 μ s
Zero-scale error
Notes 1, 2
E
ZS
10-bit resolution 1.8 V ≤ V
DD
≤ 3.6 V ± 0.60 %FSR
Full-scale error
Notes 1, 2 E
FS
10-bit resolution 1.8 V
≤
V
DD
≤
3.6 V
±
0.60 %FSR
Integral linearity error Note 1
ILE 10-bit resolution 1.8 V
≤
V
DD
≤
3.6 V
±
4.0 LSB
Differential linearity error
Note
1
DLE 10-bit resolution 1.8 V ≤ V
DD
≤ 3.6 V ± 2.0 LSB
Analog input voltage V
AIN
ANI0 to ANI2, ANI13, ANI14, ANI19 0 V
DD
V
(T
A
= ‒ 40 to +85
°
C, V
SS
= 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Voltage detection threshold V
POR
Voltage threshold on V
DD
rising 1.47 1.51 1.55 V
V
PDR Voltage threshold on V
DD
falling
Note 1 1.46 1.50 1.54 V
Minimum pulse width
Note 2
T
PW
300 μ s
T
PW
V
POR
V
PDR
or 0.7 V
Supply voltage (V
DD
)