CHAPTER 15 SERIAL INTERFACE IICA
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Figure 15 - 11 Format of IICA status register n (IICSn) (2/3)
Note
When bit 3 (TRCn) of the IICA status register n (IICSn) is set to 1 (transmission status), bit 5 (WRELn) of IICA
control register n0 (IICCTLn0) is set to 1 during the ninth clock and wait is canceled, after which the TRCn bit
is cleared (reception status) and the SDAAn line is set to high impedance. Release the wait performed while
the TRCn bit is 1 (transmission status) by writing to the IICA shift register n.
Remark 1.
LRELn:
Bit 6 of IICA control register n0 (IICCTLn0)
IICEn:
Bit 7 of IICA control register n0 (IICCTLn0)
Remark 2.
n = 0, 1
Detection of extension code reception
0
Extension code was not received.
1
Extension code was received.
Condition for clearing (EXCn = 0)
Condition for setting (EXCn = 1)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LRELn = 1 (exit from communications)
• When the IICEn bit changes from 1 to 0 (operation stop)
• Reset
• When the higher four bits of the received address data is
either “0000” or “1111” (set at the rising edge of the
eighth clock).
Detection of matching addresses
0
Addresses do not match.
1
Addresses match.
Condition for clearing (COIn = 0)
Condition for setting (COIn = 1)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LRELn = 1 (exit from communications)
• When the IICEn bit changes from 1 to 0 (operation stop)
• Reset
• When the received address matches the local address
(slave address register n (SVAn))
(set at the rising edge of the eighth clock).
Detection of transmit/receive status
0
Receive status (other than transmit status). The SDAAn line is set for high impedance.
1
Transmit status. The value in the SOn latch is enabled for output to the SDAAn line (valid starting at the
falling edge of the first byte’s ninth clock).
Condition for clearing (TRCn = 0)
Condition for setting (TRCn = 1)
<Both master and slave>
• When a stop condition is detected
• Cleared by LRELn = 1 (exit from communications)
• When the IICEn bit changes from 1 to 0 (operation stop)
• Cleared by WRELn = 1
(wait cancel)
• When the ALDn bit changes from 0 to 1 (arbitration loss)
• Reset
• When not used for communication (MSTSn, EXCn, COIn
= 0)
<Master>
• When “1” is output to the first byte’s LSB (transfer
direction specification bit)
<Slave>
• When a start condition is detected
• When “0” is input to the first byte’s LSB (transfer direction
specification bit)
<Master>
• When a start condition is generated
• When 0 (master transmission) is output to the LSB
(transfer direction specification bit) of the first byte
(during address transfer)
<Slave>
• When 1 (slave transmission) is input to the LSB (transfer
direction specification bit) of the first byte from the master
(during address transfer)
Summary of Contents for RL78/G1H
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